JPS62103735A - Program transfer device - Google Patents

Abstract

PURPOSE:To supply a program to a system in a short time by writing the program which is supplied from a host computer at low speed in a memory temporarily and transferring this written program to plural processor of the system at high speed. CONSTITUTION:The memory 1 which has storage capacity corresponding to the total capacity of a RAM where a microprogram is stored is provided and the program from the host computer 10 is written in the memory 1 (control part 2) and transferred (control part 2) to a RAM (PIP system 24) while a control signal which controls the writing of the RAM) optionally is outputted (MPM address generating circuit 4). Consequently, the transfer is carried out in an extremely short time and there is no hindrance to a signal processing.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a program transfer device used, for example, when changing processing content in a video image processing device.

[Summary of the invention]

The present invention relates to a program transfer device, in which a program supplied from a host computer at low speed is once written into memory, and the written program is transferred at high speed to multiple processors of the system, thereby transferring the program to the system in a short time. This is to enable supply.

[Conventional technology]

The applicant first applied to Video i! ! I@! Digital signal processing device that can be used for processing (Japanese Patent Application Laid-Open No. 58-215813
(see Publication No.).

In other words, Fig. 2 explains the outline of the device. In the figure, (21) is the input terminal, and (22) is the input/output control (
IOC) system, (23) is input image memory (VIM)
(24) is the signal processing (PIF) system, (25) is the address generation (PVP) thread, (26) is the output image memory (VIM) thread, and (27) is the main control (TC) thread. ) system, (28) is the output terminal.

In this device, an analog video signal from a video camera (not shown) or the like is supplied to an input terminal (21). This video signal is supplied to the IOC system (22),
V converted into predetermined digital data by D conversion etc.
Written to the IM system (23).

In addition to digital data, the IOC system (22) supplies signals for controlling the VIM system (23) from the outside, such as a clock, a dominant mode signal, an address, and a write control signal.

Also: (7) VrM system (23) D, PVP system (25
) is supplied with signals that control the VIM system (23) from inside, such as the address of digital data to be processed, write control, read mode, data selection, etc., and the data at this address is transferred to and from the PIP system (24). processing is performed. Furthermore, the data processed by the PIP system (24) is
is supplied to the IM system (26), and p is supplied to this VIM system (26).
Addresses and the like are supplied from the vp system (25). The digital data processed by this is the VIM system (26)
written to.

Zaraniko (7) VIM type (26) Nimo IOC type (22
) is supplied with the address, etc., and the resulting digital data is supplied to the IOC system (22), and the D
The signal is converted into a predetermined analog video signal by A conversion or the like and outputted to an output terminal (28).

Note that the TC system (27) supplies designation signals such as modes and methods, clock signals, etc. to each of the prefectures (22) to (26).

In addition, a start signal of a frame to be processed is supplied from the IOC system (22) to the PVP system (25), and the PVP system (
25), a processing end signal is supplied to the roc system (22).

In this way, the video signal supplied to the input terminal (21) is digitally processed and taken out to the output terminal (28), but according to the above-mentioned device, the functions necessary for processing are provided in each system. (22) to (26), each prefecture (
Since each of 22) to (26) can be provided with an independent control circuit and controlled by an independent microprogram, there is less burden on the software for each unit, and high-speed processing can be performed with a simple program. can. This makes it possible, for example, to process video signals in real time.

By the way, in the above-mentioned device, the processing content is based on PIP system (
24) and other microprograms. Therefore, by rewriting these microprograms, the contents of processing can be changed.

That is, FIG. 3 shows a specific configuration of the PIP system (24), and this PIP system (24) actually has a large number (for example, 60
Although several processor units are provided in parallel, only two of them are shown in the figure. In this figure, digital data from the VIM system (23) or (26) is input to input registers (FRA) (31a) (31b>...
・These registers are supplied to the PVP system (
25) according to the successive addresses of the VIM system (23) (26), and a predetermined amount of data required for each processor section is stored.

These registers (31a) (31b)
The data written to each calculation unit <32a)
(33a) (32b) (33b) ・
...is supplied to... Each of these calculation units is provided with an adder/subtractor, a multiplier, a coefficient memory, and a data memory, and control units (34a) (34b)...
・Perform linear and non-linear data conversion operations according to control signals from. Furthermore, this calculation result is sent to the calculation section (33a).
(33b)..., and this calculation part (3
3a) (33b) ... is PVP system (25
) is controlled according to the write address of the VIM system (23) (26), and the calculation result is written to the VIM system (23)
(26) is written to the desired part.

In this case, the control units (34a) (34b
) . . . control signals are formed according to microprograms stored in microprogram memories (MPM) (35a) (35b) . So this M PM (35a) (35h)
... is a so-called RAM configuration, and this MPM (35
a ) (35b) ... to the changed section (36a
) (36b) Each time a microprogram is written from outside through..., the contents of the process can be changed by rewriting the microprogram.

However, in that case, if the above-mentioned microprogram is created on an existing host computer (HC), etc.
From this HC, each MPM (35a) (35b)...
The transfer rate to ・is limited by the capacity of the line, and can only be sent at, for example, 500 bytes/second. For this reason, all MPMs (35a) (35b)
It takes an extremely long time to rewrite the . Furthermore, since the transfer can be performed only after the processing in the PIP system (24) or the like is completed, the HC side has to wait until the processing is completed, which may reduce the efficiency of HC usage.

[Problem that the invention seeks to solve]

The above-mentioned conventional technology has problems such as requiring an extremely large amount of time to transfer the microprogram.

[Means for solving problems]

The present invention provides a system comprising a large number of processors, each of which is driven by a microprogram, and in which the microprogram is provided in a RAM. Has a capacity note January 1)
The program from the host computer (10) is written to the memory (1) (control unit +2)), and the program written to the memo 1) is written to the RAM when desired.
(PIP system (24)) (control unit (2)), and also outputs (MPM address generation circuit (4)) a 1 control signal that arbitrarily controls writing to the RAM. It is a program transfer device.

[Function] According to this, a dedicated processor is provided, microprograms from the host computer are temporarily stored in memory, and then transferred to each microprogram memory when desired, so the transfer can be done in an extremely short time. It is possible to do this without interfering with signal processing.

〔Example〕

In MlvjJ, host computer (HC) (1
For example, the microprogram transferred from 0) in an 8-bit configuration is supplied to the 64-byte memory (1), and the write control signal from the HC (10) is supplied to the memory (1). Ru. Further, a write control signal from the IC (10) is supplied to the control unit (2), and - a signal from the control unit (2) is supplied to the memory address generation circuit (3), and the generated address is stored in the memory. 1) and the microprogram is written to an arbitrary address in the memory (1). Note that a status signal indicating the write port J function of the memory (1) is supplied from the control section (2) to the HC (10).

Further, a status signal indicating that the microprogram memory (MPM) can be rewritten is supplied from the PIP system (24) to the control unit (2). As a result, a continuous control signal is supplied from the control section (2) to the memo Shougetsu 1), and a signal from this control section (2) is supplied to the memory address generation circuit (
3) and the MPM address generation circuit (4).

As a result, the circuit (3) generates an address for sequentially reading the memory (1), and the circuit (4) generates a chip selection signal for writing the read microprogram into a predetermined MPM. Addresses for sequential writing are generated.

From Memo January 1), for example, microprograms with a 16-bit configuration are supplied to the PIP system (24), and addresses etc. from the circuit (4) are transferred to the PIP system (24).
4). Furthermore, a write control signal from the control section (2) is supplied to the pip system (24).

This is how programs are transferred, and according to this device, a dedicated line connects the mail (January 1) and the PIP system (24), and a multi-bit configuration such as 16 bits is also used. For example, if the transfer rate is set to 8 Mbytes/sec, the transfer can be performed at 16 times the speed of the conventional method.

Furthermore, when transferring the same microprogram to multiple processing processor units in the PIP system (24), the MPM
By outputting a plurality of chip selection signals from the address generation circuit (4), programs can be transferred to these chips simultaneously. This allows the program to be transferred, for example, within the vertical blanking period of the video signal,
Real-time signal processing can be performed without causing image disturbance.

Note that these transfer processes are made possible by configuring the control unit (2) and the like with a so-called microprocessor.

Furthermore, the above-mentioned program transfer can be performed using the PIP system (24
), but also for the IOC system (22), PVP system (25), etc., and this program transfer device is provided in the main control (TC) thread (27) of the prior art.

Further, the capacity of the above-mentioned memory (11) is equal to the total capacity of all MPMs.

〔Effect of the invention〕

According to the present invention, a dedicated processor is provided to temporarily store microprograms from the host computer in memory, and transfer them to each microprogram memory when desired, so that transfer can be performed in an extremely short time. It is now possible to do so without interfering with signal processing.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an example of the present invention, and FIGS. 2 and 3 are diagrams for explaining conventional techniques. (1) is a memory, (2) is a control unit, (3) is a memory address generation circuit, and (4) is an MPM address generation circuit.

Claims (1)

[Claims] For a system consisting of a large number of processors, each of which is driven by a microprogram, and in which the microprogram is provided in a RAM, the system is equivalent to the total capacity of the RAM in which the microprogram is provided. control for writing a program from a host computer into the memory, transferring the program written in the memory to the RAM at a desired time, and arbitrarily controlling writing to the RAM; A program transfer device that outputs signals.