JPH0789367B2 - Data input storage device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data input storage device used for capturing data in a video image processing device, for example.

[Outline of Invention]

The present invention relates to a data input storage device, and by allowing the data of the processed result to be fed back and written, the result data can be handed over to the next process without using an auxiliary memory, etc. It is intended to enable accumulation processing and the like.

[Conventional technology]

The applicant of the present application has previously proposed a digital signal processing device (see Japanese Patent Laid-Open No. 58-215813) applicable to video image processing.

That is, FIG. 4 is a diagram for explaining the outline of the device. In the figure, (21) is an input terminal and (22) is an input / output control (IO
C) system, (23) input image memory (VIM) system, (24) signal processing (PIP) system, (25) address generation (PVP) system,
(26) is the output image memory (VIM) system, (27) is the main control (T
C) system, (28) is an output terminal.

In this device, an analog video signal from a video camera (not shown) or the like is supplied to the input terminal (21). This video signal is supplied to the IOC system (22), converted into predetermined digital data by AD conversion, etc.
Written in 3). In addition to digital data, signals for controlling the VIM system (23) are supplied from the outside of the IOC system (22) such as clocks, control mode signals, addresses, and write control signals.

The VIM system (23) is supplied with signals for controlling the VIM system (23) from the inside of the digital data address to be processed from the PVP (25), write control, read mode, data select, etc. Data is transferred to the PIP system (24) for processing. Furthermore, the data processed by the PIP system (24) is supplied to the VIM system (26), and this VIM system (26)
Addresses, etc. from the PVP system (25) are supplied. The digital data processed by this is written in the VIM system (26).

Further, the VIM system (26) is also supplied with an address or the like from the IOC system (22), the digital data read by this is supplied to the IOC system (22), and is converted into a predetermined analog video signal by DA conversion or the like. It is converted and taken out to the output terminal (28).

The TC system (27) supplies a designation signal such as a mode and system, a clock signal, etc. to each system (22) to (26).

Further, a start signal of a frame to be processed is supplied from the IOC system (22) to the PVP system (25), and a processing end signal is supplied from the PVP system (25) to the IOC system (22).

In this way, the video signal supplied to the input terminal (21) is digitally processed and taken out to the output terminal (28). According to the above-described device, the functions required for processing are provided in each system. (22) ~ (26), each system (22) ~
Since a control circuit can be independently provided for each (26) and control can be performed by an independent microprogram, the load of software for each system is small and high-speed processing can be performed with a simple program. This makes it possible, for example, to process video signals in real time.

Furthermore, in the above-mentioned device, the contents of processing are PIP system (24)
Etc. by a microprogram. Therefore, the content of the processing can be changed by rewriting these microprograms.

That is, FIG. 5 shows a specific configuration of the PIP system (24),
This PIP system (24) is actually formed by providing a large number (for example, 60) of processor units in parallel, but only two of them are shown in the figure. In this figure, VI
Digital data from the M system (23) is sent to each processor unit (3
0a) (30b) ... Each input register (FR
A) (31a) (31b) ... and these registers are controlled by the PVP system (25) in accordance with the read address of the VIM system (23), and a predetermined amount required for each processor unit. Data is stored.

The data written in these registers (31a) (31b) ... are the arithmetic units (32a) (33a), (32b) (33b), respectively.
Is supplied to ... Each of these arithmetic units is provided with an adder / subtractor, a multiplier, a coefficient memory, and a data memory, and performs linear and non-linear data conversion arithmetic operations according to control signals from the control units (34a) (34b). Further, this operation result is obtained by the operation units (33a) (33b) ..., and the operation units (33a) (33b) ... are adjusted by the PVP system (25) to the write address of the VIM system (26). Control is performed, and the calculation result is written in a desired portion of the VIM system (26).

In this case, the control signals from the control units (34a) (34b) ... Are microprogram memories (MPM) (35a).
(35b) is formed according to the microprogram written in. Therefore, the MPMs (35a) (35b) ... Have a so-called RAM configuration, and microprograms from the outside are written in the MPMs (35a) (35b). As a result, the contents of the processing can be changed by rewriting the microprogram.

By the way, in the above device, for example, one frame of input data from the IOC system (22) is once written to the VIM system (23), and random access is made within this one frame before the internal PIP. Incorporated into the system (24). In that case, as a specific configuration, two memories 1 and 2 each having a storage capacity of one frame are provided, and the data from the IOC system (22) is alternated for each frame as shown in FIG. 6A. While writing (W), the PVP system (25) reads (R) the memory on the non-written side and supplies it to the PIP system (24). In the figure, (-) is optional.

Thereby, for example, if the processing in the PIP system (24) is completed within one frame period, the input data can be continuously processed.

On the other hand, when the processing in the PIP system (24) spans a plurality of frame periods, the data written in one of the memories 1 in an arbitrary frame period as shown in FIG. The reading is repeated during the processing period, and writing is performed in the other memory 2 during the frame period immediately after the processing is completed. IO here
If the writing from the C system (22) to the memories 1 and 2 is alternately performed as described above, the control from the IOC system (22) can be performed almost at the same time. A program for control etc. becomes simple.

However, in this device, a request is made to further pass the processed data to the next process to obtain accumulated data. In that case, if you try to pass the resulting data to the next process after performing the process that spans multiple frames as described above, for example, you can open this data as shown in parentheses in the figure. Even if it is written in the memory 2 of
Since the data from the C system (22) is written, it is destroyed and cannot be delivered.

In addition, after writing the resulting data to memory 2, IOC system (2
Writing the data from 2) to the memory 1 side is
The control from the outside that is supposed to be written alternately to 1 and 2 will be changed only at this time, and the IOC system (22) program etc. will be complicated. Further, the provision of the third memory 3 for delivery may complicate the configuration of the apparatus and further complicate the program.

[Problems to be solved by the invention]

In the above-mentioned conventional technique, when performing cumulative processing,
There is a problem that the processing result and the like cannot be easily passed to the next processing.

[Means for solving problems]

The present invention has a pair of memories (1a) and (1b), and first control means (IOC system (22)) for alternately writing external data into the two memories, and Second control means (PVP system (25)) for internally reading the data written in the memory
And a data input storage device (VIM system (23)) for supplying the data read by the second control means to the data processing means (PIP system (24)). The control means has a function of monitoring the operation of the first control means, and the data obtained as a result of the processing by the processing means is transferred from the second control means at the next writing time of the memory. By outputting a control signal for selecting the memory on the side opposite to the dominant mode signal of the first control means and rewriting to the memory on the opposite side, the resulting data is processed in the next processing. It is a data input storage device capable of transferring the processing of the means.

[Action]

According to this, since the data resulting from the processing is rewritten to the memory that was written last time, this data is not destroyed even when the next memory is written, and the data can be easily written next time. Data can be passed to the processing of.

〔Example〕

In FIG. 1, the input data from the IOC system (22) is supplied to the memory 1 (1a) and the memory 2 (1b) forming the VIM system (23), and the write address from the IOC system (22) is also supplied. Are supplied to the address selection circuits (2a) and (2b). Further IO
The control mode signal for selecting one of the memories (1a) and (1b) is supplied from the C system (22) to the selection circuits (2a) and (2b), and the write control signal from the IOC system (22) is supplied to the memory (1a). ) (1
supplied to b).

Then, the control mode signal is output from the IOC system (22) so as to alternately select the memories (1a) and (1b), so that the address is supplied to the selected memory and the write control signal is further supplied. IOC system by being output (22)
Data from the memory (1a) for each frame
It is written alternately in (1b).

Further, the address from the PVP system (25) is selected circuit (2a) (2
b) and a control signal from the PVP system (25) for selecting the memory on the same side as the one selected by the above-mentioned control mode signal or the memory on the opposite side. 2a) and (2b) are supplied. A write / read control signal from the PVP system (25) is supplied to the memories (1a) and (1b).

Therefore, for example, data from the IOC system (22) is stored in the memory (1a).
While being written alternately to (1b), the PVP system (25) outputs an arbitrary address, a control signal for selecting the memory on the side opposite to the control mode signal, and a read control signal. Causes the data in the memory opposite to the one read from the IOC system (22) of the memory (1a) (1b) to be read, selected by the data selection circuit (3) and supplied to the PIP system (24). To be done.

Also, when processing is performed across multiple frames, the same memory is selected from the IOC system (22) after writing to one memory and immediately before writing to the other memory starts. The mode signal continues to be output. Therefore, during this period, by outputting a control signal for selecting the memory on the same side as the dominant mode signal from the PVP system (25), the written data can be repeatedly used to perform a complicated processing operation.

Further, in the above-mentioned device, the data of the processing result from the PIP system (24) is supplied to the memories (1a) and (1b).

As a result, for example, as shown in FIG. 2, the data written (W) in the memory 1 in an arbitrary frame is repeatedly read (R) in the subsequent frames for processing, and the data is written in the next memory 2. At the time of, output the control signal for selecting the memory on the side opposite to the dominant mode signal, the address and the write control signal from the PVP system (25), and write the data of the result of the above processing to the memory 1. You can

Therefore, as shown in parentheses in the figure, the resulting data is passed to the next process without being destroyed by the next writing, and the passed data and the newly written data are Arbitrary reading and accumulation processing can be easily performed.

That is, FIG. 3 is a block diagram showing the flow of data. The IOC system (22) and PIP system (24) and memories (1a) (1b).
An adjusting section (10) is provided between the input section and the adjusting section (10), and the input data from the IOC system (22) and the resulting data from the PIP system (24) and respective control signals are supplied to the adjusting section (10). Data and control signals from the adjustment unit (10) are stored in the memory (1a) (1
supplied to b).

Then, the adjusting section (10) alternately sends the data and control signal from the IOC system (22) to the memories (1a) and (1b), and
Data and control signals from the PIP system (24) are sent to the designated memory.

In this way, the input data from the IOC system (22) can be temporarily stored and randomly accessed and supplied to the PIP system (24).
The data resulting from the process in 4) can be rewritten in the memory on the same side as it was read, so this result data can be easily passed to the next process, and the previous process result is used. It is possible to perform complicated processing.

Further, it is not necessary to change the control program of the IOC system (22), and it is not necessary to provide another auxiliary memory or the like.

〔The invention's effect〕

According to the present invention, the data resulting from the processing is rewritten to the memory that was previously written, so that this data is not destroyed even when the next memory is written, and is easy to write. Now you can pass the data to the next process.

[Brief description of drawings]

FIG. 1 is a configuration diagram of an example of the present invention, FIGS. 2 and 3 are diagrams for explaining the same, and FIGS. 4 to 6 are diagrams for explaining a conventional technique. (1a) and (1b) are memories, (2a) and (2b) are address selection circuits, and (3) is a data selection circuit.

Claims (1)

[Claims] 1. A first control means having a set of two memories, alternately writing data from the outside into the two memories, and reading the data written in the memory into the inside. And a second control means for supplying the data read by the second control means to the data processing means, wherein the second control means is the first control means. The operation mode of the first control means is controlled by the second control means at the time of writing the data of the result of the processing by the processing means at the next writing of the memory. By outputting a control signal for selecting the memory on the opposite side of the signal and rewriting the memory on the opposite side, the result data can be passed to the processing of the next processing means. Data input storage device.