JPS62114067A - Data input storage device - Google Patents

Abstract

PURPOSE:To easily execute a cumulative processing, etc., by writing alternately a data to two pieces of memories from the outside, reading out the written data in the inside, and rewriting the data of a result of execution of said processing, to the same memory from which it has been read out, when executing the processing. CONSTITUTION:From an input/output system (IOC)22, an input data is supplied to a memory 1(1a) and a memory 2(1b) for constituting an input image memory (VIM)23. In this case, a write address, a governing mode signal for instructing a selection of a memory, and a write control signal are also outputted from the IOC22, and the data are written alternately in the memory 1 and the memory 2. During an idle time when write is executed to the memory 1, and write is executed to the other memory, an address generating system (PVP)25 reads out said memory 1, and executes a processing, and when the IOC22 executes write to the other memory, the data of a result of processing are written in the memory of 1.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a data input storage device used, for example, in capturing data in a video image processing device.

[Summary of the invention]

The present invention relates to a data input storage device, and by making it possible to write data as a feedbank of processed data, the resulting data can be passed to the next processing without using an auxiliary memory, etc. This allows accumulation processing to be performed.

[Conventional technology]

The applicant of the present invention previously proposed a digital signal processing device (see Japanese Patent Laid-Open No. 58-215813) that can be applied to video image processing.

In other words, Fig. 4 explains the outline of the device. In the figure, (21) is the input terminal, and (22) is the input/output control (
IOC) system, (23) is input image memory (VIM)
(24) is the signal processing (PIF) system, (25) is the address generation (PVT') system, (26) is the output image memory (VIM) system, (27) is the main control (TC) system, (28
) is the output terminal.

In this device, an analog video signal from a video camera (not shown) or the like is supplied to an input terminal (21). This video signal is supplied to the IOC system (22),
V converted into predetermined digital data by D conversion etc.
Written to the IM system (23).

In addition to digital data, the IOC system (22) supplies signals for controlling the VIM system (23) from the outside, such as a clock, a dominant mode signal, an address, and a write control signal. .

In addition, to this VIM system (23), the address of digital data to be processed from the PVP system (25), write control, read mode, data selection, etc. are input from the inside of the VIM system (23).
A signal is supplied to control the address, and the data at this address is
It is transferred to the IP system (24) and processed. Further P
Data processed by the IP system (24) is transferred to the VIM system (26)
is supplied to the VIM system (26) and the pvp system (25)
The address etc. from is supplied. The digital data processed thereby is written to the VIM system (26).

Furthermore, this VIM system (26) is also supplied with addresses, etc. from the IOC system (22), and the resulting digital data is supplied to the IOC system (22), where it is converted into a predetermined analog video signal by DA conversion, etc. It is converted and taken out to the output terminal (28).

Note that the TC system (27) supplies designation signals such as mode and system, clock signals, etc. to each of the groups (22) to (26).

In addition, a start signal of a frame to be processed is supplied from the IOC system (22) to the pvp system (25), and the pvp system (
25) supplies a processing end signal to the roc system (22).

In this way, the video signal supplied to the input terminal (21) is digitally processed and taken out to the output terminal (28). Since the control circuit can be provided for each group (22) to (2G) independently and controlled by one independent microphone program, the There is less burden on the software, and high-speed processing can be performed with a simple program. This also makes it possible, for example, to process video signals in real time.

Furthermore, in the above-mentioned device, the content of processing is PIP system (2
4) etc. is determined by the microprogram. Therefore, by rewriting these microprograms, the contents of processing can be changed.

That is, FIG. 5 shows a specific configuration of the PIP system (24), and this PIP system (24) actually has a large number (for example, 60
Although several processor units are provided in parallel, only two of them are shown in the figure. In this figure, digital data from the VIM system (23) is input to input registers (FRA) (31a) (31b) provided for each processor unit (30a) (30b).
)... and these registers are supplied to PV
It is controlled by the P system (25) in accordance with successive addresses of the VIM system (23), and a predetermined amount of data required for each processor section is stored.

These registers (31a) (31b)
The data written in... are respectively processed by the calculation section (32a).
(33a).

(32b) (33b) ... is supplied. Each of these calculation units is provided with an adder/subtractor, a multiplier, a coefficient memory, and a data memory, and a control unit (34
a) (34b) Perform linear and nonlinear data conversion operations according to control signals from... Furthermore, the result of this calculation is in the calculation section (33++) (33b)
..., and this calculation section (33n) (3:
lb) ... is PVP type (25) 4. : Therefore, it is controlled according to the write address of the VIM system (26),
The calculation result is written to a desired part of the VIM system (26).

In this case, the control units (34a) (34b
)... are formed according to microprograms written in microprogram memories (MPM) (35a) (35h)... Therefore, this MPM (35a) (35b)... is made into a so-called RAM configuration, and this MPM (35a) (35b)
Changed part (36a) (36h) ・
By writing a microprogram from the outside through ..., it is possible to change the processing content by rewriting the microprogram.

By the way, in the above-mentioned apparatus, the input data from the IOC system (22), for example, one frame worth is input to the VIM system (23).
), and after enabling random access within this one frame, it is taken into the internal PIP system (24). In this case, the specific configuration is to provide two memories 1 and 2, each with a storage capacity for one frame, and to use an IOC system (22) for each frame, as shown in FIG.
The data from the
) and supply it to the PIP system (24). In the figure (
-) are optional.

As a result, input data can be processed continuously, for example, if the processing in the PIP system (24) is completed within one frame period.

On the other hand, when the processing in the PIP system (24) spans multiple frame periods, as shown in Figure B, the data written in one memory 1 during an arbitrary frame period is It is repeatedly read out during the processing period, and written into the other memory 2 during the frame period immediately after the processing ends. Here, write from the IOC system (22) to memories 1 and 2 as 1.
If you do it alternately as described above, the IOC system (22)
The control from the IOC system (22) can be performed almost equally at all times, and the program etc. for controlling the IOC system (22) can be simplified.

However, in this device, a request has been made to perform processing such as passing the processed result data to the next processing to obtain cumulative data and the like.

In that case, if you try to pass the resulting data to the next process after performing processing that spans multiple frames as described above, for example, this data will be opened as shown in parentheses in the figure. Even if it is written into the side memory 2, the data from the 10C system (22) is written in the immediately following frame, so it is destroyed and cannot be transferred.

Also, after writing the resulting data to memory 2, writing the data from the 10C system (22) to the memory 1 side requires control from the outside to write alternately to memory 1.2. The IOC system (22
) becomes complicated. Furthermore, providing the third memory 3 for transfer may complicate the configuration of the device and further complicate the program.

[Problem that the invention seeks to solve]

In the conventional technology described above, when performing accumulation processing, etc.
There have been problems such as the inability to easily pass processing results to the next process.

[Means for solving problems]

The present invention has a set of two memories (la) and (lb), and alternately writes external data to the two memories (IOC system (22)) and writes data to the memory. In a data input storage device (VIM system (23)) that outputs the input data internally (PVP system (25)) and processes it (PIP system (24)), the result of the above processing is This data input storage device is capable of passing the resulting data to the next processing by rewriting the data into the same memory where the data was successively stored.

[Effect]

According to this, since the data resulting from the processing is rewritten to the memory where it was previously written, this data will not be destroyed even if the next memory is written, and it will be easy to Data can be passed to the next process.

〔Example〕

In FIG. 1, input data from the IOC system (22) is supplied to the memory [la] and memory 2 (lb) that constitute the VIM system (23), and the input data from the IOC system (22) is
) is the address selection circuit (2a).
(2b). Further, a dominant mode signal for selecting one of the memories (la) (lb) from the roc system (22) is supplied to the selection circuit (2a) (2b),
Also, the write control signal from the IOC system (22) is
a) supplied to (lb).

Then, from the IOC system (22), the memory (la) (
By outputting a dominant mode signal so as to alternately select lb), an address is supplied to the memory on the selected side, and by further outputting a write control signal, data from the IOC system (22) is output. are written alternately to the memories (la) and (lb), for example, every frame.

Furthermore, the address from the PVP system (25) is the selection circuit (2
a) (2b) and the pvp system (25
), a control signal is supplied to the selection circuits (2a) and (2b) to determine whether to select the memory on the same side as the one selected by the above-mentioned dominant mode signal or the memory on the opposite side.

Also, write/read control signals from the PVP system (25) are supplied to the memories (la) (lb).

Therefore, for example, data from the IOC system (22) is stored in memory.
(la) and (Ib) are written alternately,
The memory (Ia) (I
Data in the memory on the opposite side to that being written is read from the IOC system (22) in b), selected by the data selection circuit (3), and supplied to the P I +) system (24).

In addition, when processing spans multiple frames, the IOC system (22) controls the selection of the same memory until just before writing to one memory starts. The mode signal continues to be output. Therefore, during this period, the PVP system (25) outputs a control signal that selects the memory on the same side as the dominant mode signal.
- Complex processing operations can be performed by repeatedly using the written data.

And furthermore, in the device mentioned above, the PIP system (24)
The data resulting from the processing from memory (1a) (1b
).

As a result, as shown in FIG. 2, for example, the data written (W) in memory 1 in an arbitrary frame is repeatedly processed (R) in subsequent frames, and the data written in the next memory 2 is processed. At this point, the PVP system (25) outputs a control signal for selecting the memory on the opposite side of the dominant mode signal, an address, and a write control signal, and writes the data resulting from the above processing to memory 1. I can do it.

Therefore, as shown in parentheses in the figure, the resulting data is passed to the next process without being destroyed by the next write, and this passed data and newly written data are It is possible to read data arbitrarily and perform accumulation processing etc. easily.

In other words, FIG. 3 is a block diagram showing the flow of data, including the IOC system (22), PIP system (24), and memory.
An adjustment unit Ql is provided between the IOC system (22) and the PIP system (22).
The resulting data and respective control signals from 4) are supplied to the adjustment unit 0ω, and the data and control signals from this adjustment unit α are supplied to the memories (la) (lb).

Then, in the adjustment unit QOI, data and control signals from the IOC system (22) are sent alternately to the memories (la) and (lb), and data and control signals from the PIP system (24) are sent to the specified memory. will be sent.

In this way, the input data from the IOC system (22) can be temporarily stored, accessed randomly, and then supplied to the PIP system (24).
Since the data resulting from the processing of the IP system (24) can be rewritten to the memory on the same side from which it was read, the resulting data can be easily passed to the next processing, and the data from the previous processing can be rewritten. You can perform complex processing using the results.

Furthermore, there is no need to change the program for controlling the IOC system (22), and there is no need to provide another auxiliary memory or the like.

(Effects of the Invention) According to the present invention, since the data resulting from the processing is rewritten to the memory in which it was previously written, this data will not be destroyed even if the next memory is written. Data can now be easily passed to the next process without any problems.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an example of the present invention, FIGS. 2 and 3 are diagrams for explaining the same, and FIGS. 4 to 6 are diagrams for explaining the conventional technology. (la) (lb) is memory, (2a) (2b
) is an address selection circuit, and (3) is a data selection circuit. Fruit flower A row product 1 mouthpiece 1 figure 4 figure 5
t-4c force゛5IJIm
Change operation, 6 F 36aR32a
35a Calculate to A 31a Di! Process, /v section (30a
034b36b R32b MPM356 Memory ω Input/Read 1 HO 1 Figure 6 PIP configuration diagram Figure 5

Claims (1)

[Claims] The device has a set of two memories, and data from the outside is alternately written into the two memories, and data written in the memory is read out to the inside for processing. By rewriting the data resulting from the above processing into the same memory from which the data was read, the resulting data can be passed to the next processing. data input storage device.