JP2557043B2 - Bit pattern detector - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention will be described in the following order.

A Industrial Field B Outline of the Invention C Prior Art D Problems to be Solved by the Invention E Means for Solving Problems (FIG. 1) F Action G Example G ₁ Description of Video Image Processing Device (FIGS. 2 and 3) Description of G ₂ bit pattern detection (FIG. 1) H Effect of the invention A Industrial field of application The present invention detects a specific bit pattern from a time series signal of 1 bit width. The present invention relates to a bit pattern detection device.

B SUMMARY OF THE INVENTION The present invention supplies an input bit time-series signal as a condition part input of a micro program controller having a conditional branch function, and detects a bit pattern according to program contents such as an instruction stored in a micro program memory and a jump destination address. However, the bit pattern can be detected by software, the circuit scale is small, and the length of the bit pattern to be detected is not limited.

C Conventional Technology Various video image processing systems have been proposed (for example, IEICE Transactions 85/4 Vol.J68-D No. 4, JP-A-58-).
215813).

FIG. 4 shows an example of this video image processing system.

That is, this is the input / output unit (1) as shown in FIG.
A memory unit (2) including an input image memory (2A) and an output image memory (2B), and a data processing unit (3).

The input / output unit (1), for example, converts the video signal from the video camera (4) into digital image data that has been A / D converted, writes this into the memory unit (2), and is processed by this memory unit (2). Read out the image data and
D-convert it back to an analog video signal, which can be
The video image can be monitored by storing it in (5) or supplying it to a monitor receiver (6).

The data processing unit (3) gives an address to the memory unit (2), reads the stored image data, applies various processing to the image data, and writes the processed data into the memory unit (2) again. To do.

The memory unit (2) has a group of images, that is, a plurality of field memories or frame memories each having one field or one frame of ease.

Writing and reading from the input / output unit (1) to the memory unit (2) are performed in units of one field or one frame which is a unit of the image.

By the way, an image processor that performs computer processing is used as the data processing unit (3). In this case, as a method for processing the image data at high speed, 2
Utilizing the characteristics of image data, which are data that are arranged in a dimensionally regular manner, a method is used in which a plurality of unit processors having the same configuration are arranged in parallel and operated simultaneously (Computer Architecture 58-3, 1985.6.21). reference).

In such a system in which a plurality of subsystems cooperate to perform one process, it is necessary to accurately manage the operation timing of instructing the process start or process branch of each processor.

In this case, in addition to the case where a plurality of processors can be controlled at exactly the same operation timing, there are many cases where it is necessary to set different operation timings, such as shifting the respective processors by a slight time and starting them. Therefore, as a method of this timing management, as shown in FIG. 5, one timing management system (100) independently operates the operation timing signal to each subsystem (101) (102) (103) (104). It is usual to send ST ₁ , ST ₂ , ST ₃ , ST _4, ... Independently for timing control.

By the way, in the case of the method of independently controlling the timing of each subsystem as shown in FIG. 5, as many timing control lines as the number of subsystems are required, and the timing management system (100) becomes large-scale. There is an inconvenience.

D. Problems to be Solved by the Invention The applicant has previously proposed an invention that solves this drawback. In the invention of the future, timing control can be performed for a plurality of subsystems by using a common timing control line, and FIG. 6 is a block diagram showing an outline thereof.

That is, the timing management system (200) uses the timing signal TS as a time-series signal via the common transmission path (300) to each subsystem (201) (202) (203) (20).
4) Supply to ...

Each of the subsystems (201) (202) (203) (204) ... has its own decoder, and each subsystem (201) (202) (203) (204) ...
・ Make original timing signal detection with.

Time series timing signal TS from management system (200)
As an example, consider the case where a time-series signal that sequentially changes as A, B, C ... Is transmitted as shown in FIG.

For this time-series signal, the subsystem (201)
Assuming that the decoder processing for generating the operation timing signal TP ₁ when the signals [A, B, C] and the following are detected, the subsystem (201) is operated as shown in FIG.
00) sends A, B, and C as the time-series timing signal TS, detects the timing, generates the operation timing pulse TP _1, and gives an instruction for processing start or processing branch.

Further, if the subsystem (202) performs a decoding process for generating an operation timing signal when a signal following [A, B, C, D] is detected, the subsystem (20
In 2), as shown in FIG. 6, when the control system (200) sends out signals TS up to A, B, C, D, this is detected and an operation timing signal TP ₂ is generated to start processing or branch processing. Etc. are given.

Further, if the subsystem (203) performs a decoding process for generating an operation timing signal TP ₃ when detecting a signal following [F, G, H], this subsystem (203)
Then, as shown in FIG. 7, when the timing signal TS is A, B, C, D,
Operation timing signal T when E, F, G, H are sent
It generates P _3, so that the instruction of the processing start, etc. is given.

By the way, the following dedicated hardware is used as a decoder for the timing signal TS provided in each subsystem. In this example, the time-series timing signal TS is 1 bit.

FIG. 8 shows an example of this decoder. The shift register (21
1), bit pattern setter (212), and comparator (21
3) consists of and.

The shift register (211) sequentially takes in the timing signal TS from the management system (200). In this case, the shift clock of this shift register (211) is the timing signal T
A clock synchronized with the transmission timing clock of S or a clock having a higher frequency than the transmission timing clock is used.

The timing signal TS is sequentially sent out bit by bit in accordance with the sending timing clock, of which a bit pattern of, for example, 5 bit length is taken into the shift register (211) in a state of being sequentially shifted by 1 bit length.

A specific bit pattern is set in the bit pattern setter (212) for each subsystem.

The comparator (213) compares the 5-bit bit pattern of the timing signal TS fetched in the shift register (211) with the 5-bit bit pattern of the setter (212),
When they match, the operation timing signal TP of the processor in which this decoder is installed is changed from this comparator (21
3) obtained from.

Now, for example, if the bit pattern set in the setter (212) is [10001], comparison is performed at the timing when the bit pattern of the shift register (211) that changes every clock of the transmission clock becomes [10001]. An operation timing signal TP is generated from the device (213).

Therefore, each subsystem (201) (202) (203)
If the bit pattern set in the bit pattern setter (212) of the decoder provided in ... Is set for each processor, the operation timing signal TP is generated at its own timing.

In this case, the timing management system (200) knows the bit pattern of the setter (212) of the decoder of each subsystem, and determines the transmission order of “0” and “1” of the timing signal TS to each subsystem. On the other hand, for example, arithmetic processing is performed so as to give a desired operation timing, and the timing signal TS is transmitted to control the timing of each processor.

In this case, the bit pattern set by the bit pattern setting unit (212) may be equal to or less than the number of bits of the shift register (211), or the number of bits may be different for each decoder.

For example, in subsystem (201), the bit pattern [10
1) is detected, the subsystem (202) starts the post-processing after detecting the bit pattern [1001]. If the time series signal 111 …… 1110111 …… 1100111 …… is sent as the timing signal TS, The subsystem (201) can be operated at the previous [101] time and the subsystem (202) at the subsequent [1001] time.

When the subsystem (201) starts post-processing after detecting [10] and the subsystem (202) starts post-processing after detecting [100], the timing signal TS becomes 111 …… 11100111 …… By sending the sequence signal, the subsystem (203) can be operated with a delay of one sending clock cycle from the subsystem (204).

However, providing the dedicated hardware as described above to each of the plurality of subsystems not only increases the cost, but also determines the length of the bit pattern to be detected depending on the number of bits of the shift register, and If there is no limit on the length, we cannot handle it.

E Means for Solving the Problems According to the present invention, a video signal processing having a plurality of unit processors having the same configuration, and performing signal processing on image data in parallel by the plurality of processors is provided. In the device, each of the plurality of unit processors includes a microprogram controller having a conditional branch function, a program for detecting a specific bit pattern from an input bit time series signal indicating an operation timing of each unit processor, and a signal processing program. A microprogram memory which stores an instruction signal and an address jump destination signal by being supplied with an address signal from the controller, wherein the microprogram controller has the input bit time series signal and the Instruction One of branch and non-branch is selected based on the conditional branch signal which is a signal, and when the branch is selected, the address signal indicated by the address jump destination signal is supplied to the microprogram memory, When a branch is selected, an address signal indicating an address obtained by adding 1 to the previous address is supplied to the microprogram memory, and each unit processor individually outputs a preset bit from the input bit time series signal. There is provided a video signal processing device characterized in that the signal processing operation is started based on a timing at which pattern data is detected.

F When operating the bit pattern, the program memory (7
From 1) to (74), when the instruction of the conditional branch is read and the target bit pattern arrives by the program software that appropriately specifies the jump destination and the next address, the step of detecting the bit pattern is skipped, and the next step You will move to the step. That is, the bit pattern is detected by software.

G. Embodiment Hereinafter, an embodiment of the present invention will be described by way of example when applied to the video image processing as described above.

The video image processing apparatus described below realizes a higher speed of data processing, and the video image processing apparatus of this example will be described with reference to FIGS. 2 to 3 prior to the description of the present invention. To do.

G ₁ Description of Video Image Processing Device FIG. 2 shows an overall outline of an example of this video image processing device. In this example, the data processing unit is mainly a processor system for calculating pixel values (hereinafter referred to as PIP). (30A)
A processor system that manages the timing of data flow management and processing such as data management and address management (hereinafter referred to as PVP)
(30B) and divide.

In the conventional data processing unit, the processing time that is the sum of the processing times of both is required, whereas if divided in this way, the processing time of the larger one will be sufficient (Japanese Patent Laid-Open No. 58-215813). See the bulletin). Therefore, in the case of this example, high-speed processing that enables video data processing to be performed in real time can be performed.

Further, in the figure, (10) is an input / output unit (hereinafter referred to as IOC), (20) is a memory unit (hereinafter referred to as VIM), which is an input image memory (VIMIN) (20A) and an output image memory (VIA).
MOUT) (20B). Reference numeral (40) is a processor (hereinafter referred to as TC) that controls execution and stop of processing.

The IOC (10) A / D-converts the video signal from the video camera or VTR, writes it as an image image in the input image memory (20A), and outputs the processed image from the output image memory (20B) as described above. Read, D / A convert, and output to a monitor.

In this case, the signal that can be input / output to / from this IOC (10) is NTSC.
It is a video signal of system or R, G, B system, and the system is designated by TC (40).

 Further, one pixel is, for example, 8-bit data.

VIM (20) has multiple frame memories, eg 12 7
The frame memory consists of 56 × 512 bytes, but in this example, the way these 12 frame memories are used is not fixed, and the input image memory is changed according to the processing purpose or the image to be processed. (20A) and output image memory (20B) can be freely allocated.

In addition, the memories are used as a set of two, and when one is in the write state, the other can be read from, and the processing from the outside of the VIM (20) by the IOC (10) and the PI
The internal processing of VIM (20) by P (30A) and PVP (30B) can be performed in parallel. In this case, multiple frame memories of this VIM (20)
The control mode signal, which is under control of (10) or PVP (30B), is generated from IOC (10), and VIM
(20) is being supplied.

The PIP (30A) and PVP (30B) basically have the same architecture, and are composed of independent processors consisting of a control unit, an arithmetic unit, a memory unit, and an input / output port. , A parallel processing method is mainly used to speed up the processing.

The PIP (30A) has, for example, 60 PIP processors and several sub processors, and processes image data from the VIM (20) or internally generates image data. This PIP (30
The clock of A) is supplied from TC (40).

PVP (30B) has about 30 processors and VIM (2B
Controls the flow of image data inside the VIM (20) such as the allocation and collection of pixel data from 0) to the PIP (30A).

That is, the PVP (30B) generates the address data and control signal to the VIM (20), and outputs these to the VIM (2
0), generate PIP (30A) input / output control signals and other control signals, and supply these to PI.
Supply to P (30A).

The input image memory (20
Not only when processing only the data from one frame in (A) and writing the processed data to the output image memory (20B), but using data that spans multiple frames from multiple frame memories. It may also be processed.

And the number of calculation digits in PIP (30A) and PVP (30B) is 16
Bits are standard, and the processing speed of the image data processing is such that processing of one frame of image data can be performed within one frame, that is, real-time processing. However, there are some processes that require a processing time of one frame or more.

In this case, the image data processing by PIP (30A) and PVP (30B) is performed in synchronization with the frame. For this reason, PVP
A processing start timing signal PS (which goes to a low level when the processing is started) synchronized with the frame is supplied to the (30B) from the IOC (10). On the other hand, from the PVP (30B), a signal OK indicating that one process is completed is supplied to the IOC (10).

Signal PS is real-time processing (1 frame of data is 1 /
Processing at 30 seconds), at the beginning of each frame, otherwise at the beginning of the next frame after the signal OK and at the beginning of the frame specified by the user.

The signal OK is output from the core processor of the PVP (30B), which controls the timing of the processing system, of the PVP (30B) processor when the processing is completed.

In other words, in the core processor of this PVP (30B), IO
It is detected programmatically that the processing start timing signal PS from C (10) has become low level. And the signal
When it detects that PS goes low, this processor starts running, and the other processors in PVP (30B) and PI
A timing signal TS is issued to P (30B) by a program, an address is supplied to VIM (20), image data is read from VIM (20), and processing is performed by PIP (30A).

FIG. 4 is a block diagram of this timing management part. As described above, the timing management processor (50) is provided as the core processor in the PVP (30B). Then, the processing start timing signal PS is supplied from the IOC (10) to the processor (50), and the processing end signal OK is sent from the processor (50) to the IOC (10).

When the processor (50) detects that the processing start timing signal PS has become low level, it outputs a 1-bit width time-series signal as the timing signal TS to this PV.
Send to other processors (51) (52) (53) in P (30B) and PIP (30A) processors (61) (62)
・ Send to (66). In this case, the 60 processors in the PIP (30A) are controlled in groups of 10.

Each processor (51) (52) (53) and (61) to (66)
Then, the bit pattern detection unique to each processor is performed by software from the bid time series signal which is this timing signal.

Description of G ₂ Bit Pattern Detection FIG. 1 shows an example of the program memory addressing circuit of each processor which controls the bit pattern detection and the processing subsequent to this detection.

In the figure, (70) is a microprogram controller, for example, Am2910 manufactured by AMD. (71) ~
(74) is a microprogram memory. The addresses of the micro program memories (71) to (74) are generated from the micro program controller (70) via the register (75).

The micro program memory (71) provides an instruction bit for selecting one of a plurality of instructions of the micro program controller (70), which is transmitted via a register (76) to an instruction terminal I of the controller (70). Is supplied to.

Further, (77A) is a selector to which a plurality of desired 1-bit information is supplied, and one of them is selected by the information read from the microprogram memory (72). The 1-bit information from the selector (77A) is supplied as a condition code to the program controller (70) via the inversion control circuit (77B). , Information for selecting the address supplied to the direct input terminal D or another address.

In this case, the inversion control circuit (77B) is supplied with 1 bit of the output from the memory (72), and the 1 bit is "1".
, The input data bit is output as it is, and when 1 bit is “0”, the input data bit is inverted and output.

From the micro program memory (73), for example, "go
Information such as the destination address of the "to sentence" and the number of Do loops are obtained, and this is latched in the register (79 ₁ ).

Information on microinstructions is obtained from the microprogram memory (74) and given to the arithmetic unit via the register (78).

The micro program controller (70) is adapted to enable one of the three enable signals PL, VECT, MAP according to the instruction bit. Therefore, _one of the registers (79 ₁ ) to (79 ₃ ) is enabled by the instruction bit, and the address latched therein becomes the direct input of the terminal D. In most instructions, PL is enabled. However, whether to select direct input in the instruction depends on the condition code from the inversion control circuit (77B).

The 1-bit width time-series signal, which is the timing signal TS, is used as one input information of the selector (77A), and when the bit pattern detection program described later is executed, the time-series signal is programmed by the selector (77A). To be done. However, one bit to the inversion control circuit (77B) is programmed to be appropriately selected.

In this example, "conditional branch" is used as an instruction for bit pattern detection.

In this "conditional branch" instruction, if the condition code is "1", it is a non-branch, and the address obtained by adding 1 to the previous address as the next address is obtained from the microprogram controller (70). on the other hand,
If the condition code is "0", branch is performed,
Address of the jump destination has been programmed into the microprogram memory (73) as a next address register (79 ₁₎ The jump destination address is input to the D terminal via is obtained from the microprogram controller (70).

In this case, as described above, the Am2910 performs the branch and outputs the jump destination address only when the condition code is “0”. Therefore, when the input bit time series is “1”, the Am2910 performs the branch. 1 sets the 1-bit polarity data from the memory (72) to the inversion control circuit (77B) to "0" to invert the polarity and perform branching.

In summary, instructions are conditional branches,
If the jump destination is JA (= numerical value) and the polarity data is "1", branching is performed when the external input bit time series is "0", and non-branching when it is "1". Hereinafter, this instruction group will be referred to as “IF φ JP JA”.

Similarly, when the polarity data is "0", branching is performed when the input bit time series is "1", and when the input bit time series is "0", no branching is performed. Hereinafter, this instruction group is referred to as "IF 1 JP JA".

From the above, the bit pattern [A ₀ , A ₁ , ... Ai ...
To detect An _-1 ] (Ai is 0 or 1), the following instruction group may be written in the micro program memories (71) to (74).

However, each Pi should be given appropriately.

When a bit pattern [A ₀ , A ₁ ... Ai ... An _-1 ] arrives in the time series of the input bits by this program, the program for this bit pattern detection is exited, and the process proceeds to the nth and subsequent steps. go. That is, the steps from the nth address onward are not proceeded until the bit pattern arrives,
The bit pattern is always detected, and only when the bit pattern is detected, the process proceeds to the next n and subsequent addresses.

For example, the program for detecting the bit pattern [11001101] is as shown in the following table.

With the program above, the input bit time series [11
[001101] has arrived, the process will proceed to address 8 and thereafter.

As described above, the bit pattern is detected by software. Therefore, if the bit pattern to be detected is changed in each processor as described above, each processor starts operation at different timing.

The bit pattern detecting device of the present invention can be used not only for detecting the timing control signal of the video image processing device as described above but also for various purposes.

H According to the present invention, a microprogram controller having a conditional branching function and a microprogram memory are used, and an input bit time series is input to the condition part of the microprogram controller, so that a bit pattern can be obtained by software. Can be detected.

Therefore, the microprogram controller and the microprogram memory originally possessed by the processor can be used, and the hardware scale can be small. Further, there is no limitation on the length of the bit pattern to be detected, and there is an advantage that it is versatile.

[Brief description of drawings]

FIG. 1 is a block diagram of an example of the device of the present invention, FIG. 2 is a block diagram of an example of a video image processing device to which the present invention is applied, FIG. 3 is a block diagram of an example of a main part thereof, and FIG. FIG. 5 is a block diagram illustrating an example of an image processing apparatus, FIG. 5 is a block diagram illustrating a general timing control method, FIG. 6 is a block diagram illustrating an improved timing control method, and FIG. FIG. 8 is a block diagram showing an example of a timing signal decoder for the purpose of explanation. (70) microprogram controller, (71) - (74) microprogram memory, (75), (76), (78), (79 ₁₎ to (79 ₃₎ is a register.

Claims (1)

(57) [Claims] 1. A video signal processing apparatus having a plurality of unit processors having the same configuration, wherein the plurality of processors perform signal processing on image data in parallel, wherein each of the plurality of unit processors is a signal processor. , A micro program controller having a conditional branch function, a program for detecting a specific bit pattern from an input bit time series signal indicating the operation timing of each unit processor, and a signal processing program are stored, and an address signal is sent from the controller. And a micro program memory for supplying an instruction signal and an address jump destination signal to the controller by being supplied, and the micro program controller outputs the input bit time series signal and the conditional branch signal which is the instruction signal. Basis One of the branch and the non-branch is selected, and when the branch is selected, the address signal indicated by the address jump destination signal is supplied to the microprogram memory, and when the non-branch is selected, the address is returned to the previous address. An address signal indicating an address to which 1 is added is supplied to the microprogram memory, and each unit processor is based on the timing at which data of a preset bit pattern is detected from the input bit time series signal. A video signal processing device, characterized in that it starts the signal processing operation.