JPH0370006A - Sequence controller - Google Patents

Abstract

PURPOSE:To perform multi-bit input/output control in real time by performing a series of main sequence and subsequence attached on each process in parallel. CONSTITUTION:The controller is equipped with the main sequence 1-10 which handle a series of sequence, the subsequence 12 which handles individual sequence in the process started up with the main sequence 1-10, an arithmetic and logic part 11 which processes encoded data, and a universal processor 100. Parallel type sequence control can be operated smoothly by making access a micro code part to control input/output and a control memory encoded to a time base and control I/O data with the above four devices, and also, the I/O control of multi-bits can be performed at the same time. In such a way, fast sequence control can be realized by incorporating sequence control into the hardware.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a sequence controller used for controlling component mounting machines, robots, copying machines, etc.

[Prior art] In recent years, in systems that include a large number of sequence controls such as robots and FA type equipment, the number of control items has increased in order to support complex control operations. Action is now required.

In order to meet these demands, conventional methods have been to increase the speed of software and CPU.

Here, the sequence control that controls the multi-bit I/O section is performed using conventional general-purpose processors and CPs.
The operation of the system configured with U will be described with reference to FIG.

The CPU (61) creates jobs for sequence control and manages other peripherals, CPU2 (62) is used to manage sequences, and the 2-bot RAM 63 is used for CPU (61). and C.P.
It is configured as a communication means for U2 (62). That is,
The CPU2 (62) manages the sequence time and communicates the Ilo status to the CPU1 (61) at a certain period of time using the two-vote RAM63, and the CPUUI (61) accordingly sends the next message to the CPU2 (62). Send the sequence data. This realizes a sequence controller and controls a multi-bit I/O section.

Incidentally, a CPU is originally good at processing calculations and making complex judgments, but is not suitable for executing simple sequences that do not require complex calculations or judgments.

[Problem to be Solved by the Invention] However, in the above configuration example, the CPU
(62) When communication is frequently performed between the two, the execution time is slow as described above, even though the sequence is simple, and as a result, the control time becomes dense, so the CPU is used only for sequence control. processing time is spent,
You may not be able to do other jobs.

As described above, when a CPU is used for sequence processing, there is a possibility that a time delay occurs, causing a synchronization difference in the flow of the sequence, and there is a limit to the pursuit of high-speed processing and operation.

The present invention was made in order to eliminate the above-mentioned problems, and an object of the present invention is to provide a sequence controller that implements sequence control in hardware and enables high-speed sequence control.

[Means for Solving the Problems] The sequence controller of the present invention processes a main sequence that controls a series of sequences, a subsequence that controls individual sequences within a process started from the main sequence, and coded data. The microcode section for controlling input/output and the control memory encoded in the time axis and control I/O data are accessed by the above four devices. By doing so, parallel sequence control can be operated smoothly, and multi-bit I/O control can be controlled at the same time.

[Operation] This device enables control of a series of main sequences and sub-sequences incidental to each process to operate in parallel in control equipment such as robots and FA equipment. As shown in the figure, this corresponds to the top when the control equipment is converted into a process control system, and the subsequences extend from the top to the next level.

[Embodiment] Fig. 2 shows an embodiment of the sequence controller of the present invention, in which the MPU/O0 and l~
It is composed of a main sequence device up to IO, a sub-sequence unit 12, and an I/O control unit 11.

First, the initial state flow of this device is that the MPU/O0 writes the MAX value for the sequence clock to the sequence capture 2 as data, and then the I
/O to control unit 11 AO~A13, BO~
Set data direction information for B13, CO to C13, and DO to D13.

Next, control data for the device to be sequence controlled is written from the memory table ROM 8 to the main sequence data register 5. The data structure here, as shown in (c) in FIG. 5, consists of a sequence address H, a pulse offset G, a count data I, and a process value J, which is 2 words! It is stored in sequential blocks. The pulse offset G is set to an offset value of 600 from O shown in the time chart of FIG. That is, the offset value of the next sequence is 5
It is set to 00. Next, the sequence address H sets the width of the main sequence, and the end of the process is managed based on this count data width. Sequence address H defines the upper five bits of the address of the program memory area that describes this main sequence, and process value J indicates 1-bit data for selecting process 1.2.

When the data is loaded into the main sequence data register 5, the offset data of two words of the initial main process data is loaded into the offset register 1 of the start main process controller 6, and the offset data of the first main process data is loaded into the offset register 1 of the start main process controller 6. count data register l
The data at sequence address H is loaded into subsequence unit 12. Then, the 13-bit address counter (not shown in FIG. 5(b)) is set to the sequence address 15. In this example, a line counter 16 is configured, and in this example, 25
6 words are transferred.

At this time, each subprocess is configured with 32 bits - 2 words of memory, and the function code memory (16 bits) shown in FIG.
It has a function data memory (16 bits) shown in Figure (d), and its bit configuration is as shown in Figures (c) and (d).
As shown, A: microcode area, B: NopS
C: Sub-process offset data (pulse count)
, D = 14-bit input/output data, E: boat selection (4 boats).

Then, counter 1 (13) in FIG. 3 is cleared.

When 256 words of sub-process data are transferred, process unit 1 (17) is cleared, and at the same time, with process value J=O, 32 bits of data in the RAM at address 00 are transferred (memory step in Figure 3). The sub-process offset data (FUNCI) of function code C in FIG. 5(c) is loaded into data 19, and the ABDE at address 00 of function data 21 in FIG. 3 is loaded into the respective set registers. When the loading is completed, process unit 1 (17) is incremented and holds the address value of Ol.

Next, in order to prepare the process unit 2, the main sequence data memory address of the start main process controller 6 shown in FIG. 2 is incremented by 1, and the main process 2 is loaded.

Works the same as process 1, but offset register 6
Then, the data added to the offset data loaded immediately before is loaded into the offset register 2. Further, the count data is loaded into the count data register 2, and the counter 2 (13) in FIG. 3 is cleared.

The above operations complete the initial setting of the sequence controller and wait for the entire process to start.

Next, the operation of this device will be explained with reference to the time chart shown in FIG. When the start signal is activated, the sequence counter 3 starts counting up, and when the count value reaches 600, it matches the offset register 1 of the start main process controller 6, and the sub-process 1 is activated. When the subprocess 1 is started, the counter 13 in FIG. 3 starts counting up. In this example, when 50 pulses are counted, it matches the sub-process offset data at the beginning of process l, and its IIHJi
The I/O control data loaded into the function data 21 in FIG. 3 is loaded into the ALU 23. In this example, AOA-Al1 is set to the bin defined as the output by the A microcode and becomes "H". after that,
Process unit l is at address 01, and as soon as the data processing at address 00 is completed, the RAM of process l is
The 32-bit data from the area is set to the function data 20 and 21 in FIG. 3 using a routine similar to the initial setting. The data of C at this time is added to the immediately previous value of C to prepare for the next time coincidence. In this example, the immediately preceding subprocess offset data is 50 and address 01 is 75, so a match of 125 is waited for.

In this way, process l repeatedly increments the address and performs I/O control without time lag.
When the data in 13-1 in Figure 2 and the pulse offset register match, the main process ends, and at the end, the data for starting the third main process from main sequence data 5 is set as in the initial setting. Set using the following method.

As mentioned above, if there is only one main process, it can be configured with a conventional MPU, but if another process is started at the same time, for example, if main processes 1 and 2 in time chart 1 overlap, this configuration can be used. And even more control over efficiency is possible.

Assume that main process 2 is started at tioo sequence clock, subprocess 1 of main process 2 is started at 50, and subprocess 4 of main process 1 is started at t ioo sequence clock.
If it is 550 (sub-process offset), control at the same time is required. For example, M
It is not possible to simultaneously control 28 bits using two PUs as in this example.

However, according to this configuration, simultaneous control of 28 bits is also possible, and complicated software control is not required.

In this example, the MAX of the main process is set to 2 and the MAX of the subprocess is set to 128, but this can be easily improved by adding bits to the address counter.

For reference, it is also possible to start a completely different main process as shown in the table below.

[Effects of the Invention] As explained above, by controlling a series of main sequences and sub-sequences attached to each process in parallel, multi-bit input/output control can be performed in real time. It enables input/output control that does not depend on the system, and allows many processes to operate simultaneously.

[Brief explanation of drawings]

FIG. 1 is a flow diagram showing the processing sequence of the present invention, FIGS. 2 and 3 are control book diagrams for the main sequence and sub-sequence in the sequence controller of the present invention, and FIG. 4 is a flowchart showing the processing sequence of the present invention. and a time chart showing the operation in the control block diagram of FIG.
The figure shows each memory configuration, and FIG. 6 is a block diagram showing an example in which a CPU is used for sequence processing. l...Timing generator, 2...Sequence capture 3...Sequence controller, 4...Read/Write controller, 5...Main sequence data, 6...Start main process controller, 7...
・Count data latch, 8...ROM, 9...RAM. /O...Data direction controller, 11.
・I/O control unit, 12... Subsequence unit, 13... Counter 1.2.14... Comparator,
15... Sequence address, 16... Line counter, 17... Process unit, 18... Process unit 2. 19.20...Memory step data, 21.22.
...Function data, 23...ALU. 24...read/write control, 25...D
MA control.

Claims (1)

[Claims] (1) A main sequence that controls a series of sequences, a subsequence that controls individual sequences within a process started by the main sequence, a logic operation unit that processes coded data, and a general-purpose processor; Parallel sequence control can be operated smoothly by accessing the microcode section for output control and the control memory encoded in the time axis and control I/O data using the above four devices. A sequence controller characterized in that the sequence controller is configured such that multi-bit I/O control can be performed at the same time.