JPH0566939A - Block operating instruction executing device for integrated circuit microprocessor - Google Patents

Abstract

PURPOSE:To carry out an instruction called a block operation or a string operation which repeats the same operation with high efficiency by carrying out each unit operation on a pipeline for the block operation instruction. CONSTITUTION:An instruction decoding means can decode a block operation instruction which has the contents to carry out repetitively the same unit operation. An instruction executing means repeats the unit operations forming the block operation instruction in a pipeline control system based on the decoding result of the instruction decoding means. Then the continuous unit operations, e.g. the unit operations (1) and (2) are turned into a pipeline when a microprocessor carries out a block comparison instruction. As a result, the availability is improved for a bus device where an integrated circuit microprocessor is connected to an external storage and an input device. Then the total throughput of the integrated circuit microprocessor is improved.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an integrated circuit microprocessor and, more particularly, to an instruction execution device capable of executing a "block operation" instruction, which is characterized by repeating the same operation a plurality of times.

[0002]

BACKGROUND OF THE INVENTION Many integrated circuit microprocessors include
It has an instruction or group of instructions called "string operation" or "block operation". Such an instruction has the content that the same operation is repeatedly performed by one instruction. Throughout this specification, such instructions will be referred to as "block manipulation instructions."
Further, the same operation that is repeatedly executed in this "block operation instruction" is referred to as a "unit operation". In executing these instructions, unlike the case of repeatedly executing the instructions having the same processing, the instruction fetch operation and instruction decode operation for each instruction are not necessary. Therefore, the block operation instruction mainly operates a data structure, such as a character string, a buffer, or a data frame, which is larger than the data such as bytes and words which can be normally processed by the microprocessor in the main memory, by one instruction. It is suitable for various cases, and various things are practically used, from simple data structure movement called block transfer to character string comparison and batch data input / output called block input / output.

As described above, since the block operation instruction repeatedly executes the same unit operation with one instruction, there is no reduction in speed due to the instruction fetch operation and instruction decode operation as compared with the case where the instructions are combined, It is a very efficient process.

[0004]

However, when the execution of the block operation instruction is considered from the viewpoint of bus operation, it is not always efficient. That is, when the repeated operation is simple, a lot of time is not required for the arithmetic processing for its execution, so that the bus is used up to its performance limit and the usage efficiency is high. However, if the repeated operation is complicated, it takes a lot of time to perform the arithmetic processing for its execution, and the bus is left unused during this processing time. Efficiency is low. As a result, the throughput of the integrated circuit microprocessor as a whole is also reduced.

In view of this point, an object of the present invention is to improve the efficiency of use of a bus device connecting an integrated circuit microprocessor with an external main memory device and an input / output device when executing a block operation instruction. By increasing it, it is intended to improve the throughput of the integrated circuit microprocessor as a whole.

[0006]

In order to solve the above problems, the present inventor has paid attention to a pipeline control system, and can utilize this control system to efficiently execute a block operation instruction. I have to.

[0007] Here, in the pipeline control method which is generally performed, an instruction execution process is performed by, for example, reading an instruction code (instruction fetch), decoding an operation (decoding), executing an instruction, and executing a bus accompanying instruction execution. By dividing each of the input / output operations into four parts and letting these partial processes be handled by an independent device, each device is dedicated to the partial process for one instruction, and as a whole, four consecutive commands are simultaneously executed in parallel. I'm trying to run it. By doing so, the throughput of the integrated circuit microprocessor as a whole can be increased up to four times in this example by the amount that parallel processing of instructions and simultaneous processing are achieved as compared with the case where pipeline processing is not performed. .. Such a pipeline control method has been established as an important speed-up method, and its standard methods are subdivision of processing, independence of subdivided processing as a device, and connection between devices, and By performing processing by sequentially passing the data to be processed to the subdivided multi-stage device from the front stage side, the processed data is output from the last stage device one after another. is there. The point to be noted here is that the pipeline control method established as a speed-up method is
It is performed in units of instructions, and does not target each operation in one instruction.

In the present invention, the pipeline operation method is applied to the unit operation repeatedly executed in the block operation instruction, whereby the block operation instruction can be efficiently executed. To this end, the instruction execution device of the integrated circuit microprocessor according to the present invention is capable of decoding a "block operation" instruction having the content of repeatedly executing the same unit operation, and a decoding result by the instruction decoding means. And an instruction executing means for repeatedly executing the unit operation constituting the block operation instruction by a pipeline control method.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An example in which the present invention is applied to an integrated circuit microprocessor realized on a CMOS integrated circuit will be described below with reference to the drawings.

FIG. 1 mainly shows the part of the instruction execution device in the integrated circuit microprocessor of this embodiment.
In this figure, 1 is an address bus, 2 is a control bus,
A data bus 3 is connected to the bus interface device 4. The bus interface unit 4 is connected to the instruction execution unit 6 via the internal address bus unit 5 and the like. The configuration of each of these parts will be described below.

Address bus 1 is a 25-bit signal line group capable of transmitting information unidirectionally from an integrated circuit microprocessor to an external storage device and an input / output device (both not shown). Of these, 23 bits are a true address signal and 2 bits are a byte operation output. The integrated circuit microprocessor of this example allocates addresses in units of bytes (8 bits), but since the data bus 3 is set to have a 16-bit width as described later, the upper or lower 8 of the data bus 3 is It has an output for manipulating bytes that indicates the validity of each of the bits. A 23-bit address makes it possible to access a 16-Mbyte (8-Mword) main memory. In the case of the integrated circuit microprocessor of this example, a 32-bit address is internally generated, but due to the assembly technique, only the address corresponding to a total of 24 bits including the 2-bit byte operation output is output. There is. The address of the input / output device can be designated by using only the lower 16 bits of the address of 24 bits. Whether the address is the main memory device address or the input / output device address is determined by the output signal MEM / of the control input / output of the control bus 2 described later.
It is determined using IO #. Address bus 1
When a bus hold request arrives from a bus master (not shown) outside the integrated circuit microprocessor and this is accepted by the bus interface device 4,
A tristate drive circuit is used so that a high impedance state is achieved.

Control bus 2 Output signal group WR / RD #, DAT indicating the type of bus operation
/ C #, MEM / IO #, 3 bits of output signal group RWT #, ASSTB #, DCS # indicating output timing of address bus, data bus, etc., and bus cycle length from the outside And 2 bits of input signal groups NXTA # and BREADY # for controlling timing, and an input signal HL for accepting a bus hold request.
Output signal H indicating acceptance of DREQ and request
It has 2 bits of LDACK. The control bus 2 is
When a bus hold request arrives from a bus master external to the integrated circuit microprocessor and is accepted by the bus interface device 4, an output signal HLDACK is output.
A tri-state type drive circuit is used so that the 6-bit output signal other than that can be put in a high impedance state.

Data bus 3 is a 16-bit signal line group capable of bidirectionally transmitting information. The information transmission direction is specified by the output signal WR / RD # of the control input / output signal group, as described above. In the integrated circuit microprocessor of this example, the internal number is 3
Due to the 2-bit configuration, the internal 32-bit data is processed using 2 bus cycles of the external bus. In the case of processing 8-bit data, only the lower or upper 8 bits of 16 bits are used. Which of the upper and lower bytes to use is specified by the byte operation output of the address bus 1 described above. The bus drive circuit of the data bus 3 is composed of a tri-state type circuit, and
When the bus hold request arrives by the input signal HLDREQ supplied from the master and is accepted by the bus interface device 4, the data bus 3 can be set to the high impedance state.

Bus interface device 4 The address bus 1 and the control bus 2 described above are taken as a unit of a series of indivisible operations called "bus cycle".
And the data bus 3 are integrated and operated to perform data transmission / reception between the integrated circuit microprocessor and the external main memory and input / output device. It also performs the operations required to share the bus device with other bus master devices such as microprocessors. The bus interface device 4 of this example has the following bus cycles normally required.

Main Memory Read Bus Cycle Main Memory Write Bus Cycle I / O Device Read Bus Cycle I / O Device Write Bus Cycle Hold Response Bus Cycle Interrupt Response Bus Cycle Processor Stop Bus Cycle

In addition to these, in order to efficiently execute the block operation instruction, the above-mentioned modified bus cycles have the following bus cycles from (10) to (10).

Block read / write cycle Block input / output cycle (10) Read change write cycle

The bus interface unit 4 is a data interface.
Bus control PLA device and address bus control PL
A bus control state machine centered on the A unit is provided to control each bus cycle described above. Each bus cycle is implemented as a logical term consisting of bit strings unique to each PLA.

Internal address bus device 5 A 32-bit internal bus device for the purpose of address transfer from the instruction execution device 6 to the bus interface device 4.

Instruction Execution Device 6 This device controls instruction execution. In the following description, only the part related to the pipeline processing in the block operation instruction will be described. The other components can be configured similarly to a general integrated circuit microprocessor.

The instruction execution unit 6 is an address generation unit 60.
1, counter device 602, register device 603 and A
The LU device 604 is provided. Each of these parts is controlled by the first control device 611, the second control device 612, the third control device 613, and the fourth control device 614, respectively. These first to fourth control devices 61
Of the first, 612, 613 and 614, the first to third control devices 611, 612 and 613 are the first to third pipeline register devices 621, 622 and 62, respectively.
Drive control is performed by the first state machine 605 via the control unit 3 of FIG. Further, the fourth controller 614 is drive-controlled by the second state machine 606 via the fourth pipeline register device 624. The address generation device 601, the counter device 602, the register device 603, and the ALU device 604 are the internal bus device 607.
Are connected to each other via. Further, the instruction execution device 6 includes a detection device 608 for detecting the counting operation of the counter device 602. The configuration and operation of each of these parts will be further described below.

(Address generation device 601) Generates an address required for instruction execution based on the register value supplied from the register device 603 instructed by the instruction. The address generator 601 is mainly composed of a 32-bit adder, and four 32 bits that temporarily store the input and output of the adder are provided.
Bit temporary register, 10 32-bit base address registers that are always added even if not instructed by an instruction, and verification of generated address 1
It contains zero 32-bit attribute registers.

(First control device 611) This is a device for controlling the adder, the register, etc. of the address generation device 601, and is composed of a random logic circuit. The control command to the first control device 611 is sent via the first pipeline register device 621 to the first state machine 60.
It is supplied from 5.

(First Pipeline Register Unit 62
1) A temporary storage device for temporarily storing a control command for the first control device 611 output from the first state machine 605 and delivering it to the first control device 611 at a necessary time.

(Internal Bus Device 607) This is an internal bus device which is composed of two 32-bit internal bus devices and is capable of transferring data of up to 64 bits at a time, and employs a precharge system.

(Counter device 602) "Block operation"
It is a device for controlling repetitive operations peculiar to an instruction. The block operation instruction is activated by placing the following data in the register device 603.

Number of block operations Start address of the first main memory address that is the transfer destination if necessary Start address of the second main memory address that is the transfer source if necessary

The counter device 602 of this example receives the information regarding the number of block operations, and counts down each time a unit operation of a block operation instruction is performed.

Here, if each unit operation of the block operation is pipelined, the above-mentioned number of block operations is examined by the detection device 608 at the stage when it is sent to the counter device 602 via the internal bus device 607, and the unit operation is performed. It may be necessary to count down in advance. This depends on the type of target block operation instruction,
Due to the pipelining, it takes time between the activation and completion of the unit operation, and the detection device 608 detects that the unit operation is the unit operation related to the last repetition after the activation of the last unit operation. This is because the activation of the next unit operation cannot be stopped.

(Second control device 612) Counter device 6
This is a device for controlling the load of the data including the information on the number of times of the block operation for 02 and the count down operation thereof, and is configured by a random logic circuit. The control command to the second control unit 612 is sent to the first control unit via the second pipeline register unit 622.
State machine 605.

(Second pipeline register device 62
2) It is a temporary storage device for temporarily storing the control command output from the first state machine 605 to the second control device 612 and delivering it to the second control device 612 side at a necessary time.

(Detection Device 608) This is a device for detecting that the counter device 602 has finished counting down the specified number of times, and is mainly composed of a precharge type circuit. That is, the end of the countdown of the number of loaded block operations is detected. When this end is detected, the final end signal 2S is sent to the first state machine 6
Output to 05.

(Register device 603) A memory device composed of 34 32-bit registers. Reading from two registers at the same time, reading from one register which is not the same and writing into one register, Alternatively, it is possible to perform either the read operation for one register or the write operation for one register. As described above, the block operation instruction is activated by placing the following data in this register device 603.

Number of block operations Start address of the first main memory address that is the transfer destination if necessary Start address of the second main memory address that is the transfer source if necessary

(Third control device 613) Register device 6
It is composed of an address decoding unit for 03 and a read / write control unit. It is composed of a random logic circuit, and the control command to the third controller 613 is
The first via the third pipeline register unit 623
State machine 605.

(Third pipeline register device 62
3) A temporary storage device for temporarily storing a control command for the third control device 613 output from the first state machine 605 and delivering it to the third control device 613 at a necessary time.

(ALU device 604) It is composed of an ALU main body for arithmetic and logic operations, six temporary storage registers for temporarily storing input / output data, and a circuit portion for detecting and holding a specific condition. It is possible to accept a maximum of three 32-bit data and one 5-bit data for the temporary storage register and perform arithmetic operations and logical operations. The ALU device 604 detects a specific condition set by the fourth control device 614, holds it as a flag therein, and generates a block operation interruption condition signal 1S. The interruption condition signal 1S is used to detect a specific condition in the block operation instruction and interrupt the block operation.

(Fourth Control Device 614) ALU Device 60
4 controls the temporary storage register operation, ALU calculation type and detection condition. This fourth control device 61
4 is the fourth pipeline register 6
It is supplied from the second state machine 606 via 24.

(Second state machine 606) It is composed of a PLA circuit, an input / output register connected to this input / output, and a feedback circuit connecting the input / output registers. This state machine is for controlling the ALU device 604. Simple operations such as addition, subtraction, logical sum, logical product, etc. can be performed in one operation by sending a control command. On the other hand, multiplication, division, shift, rotate operation, etc. combine some control commands, and the ALU device 60
The control is performed after judging the interruption condition signal of the block operation from 4. During execution of the block operation instruction, the ALU operation associated with the repetition of the block operation unit operation is controlled.
The control of this ALU operation has the main purpose of detecting the interruption end condition of the block operation.

(First state machine 605) A PLA circuit, an input / output register connected to the input / output of the PLA circuit, and a feedback circuit connecting the input / output registers. This state machine is a device intended to control the first to third control devices 611, 612 and 613 except the ALU device 604 and to communicate with the bus interface device 4. During execution of the block operation instruction, the source of repetition of the unit operation of the block operation is controlled. In this case, since it is necessary to cooperate with the second state machine 606 that controls the ALU device 604, the synchronization signal is also sent to this second state machine. In the case of a block operation, the final end condition is an end condition detected by the detection device 608, but there is also a condition detected by the ALU device 604 as an interruption end condition, and the first state machine 605 receives both of them.

Next, the contents of each signal shown in the figure will be listed.

Code Content 1S This is a block operation interrupt condition signal indicating that the block operation interrupt termination condition is satisfied. In the case of this example, the interruption end condition is a match or a non-match of comparison in the ALU device 604, and the content of the interruption end condition is determined by the second state machine 606. It is the end condition of the block operation indicating that the final end condition of the 2S block operation is satisfied. In this example, the final termination condition is that the count result in the counter device 602 becomes zero. 3S A signal group to the third pipeline register device 623, which is composed of a control command to the third controller 613 and a timing control signal to the pipeline register device 623. 4S A signal group to the second pipeline register device 622, which is composed of a control command to the second controller 612 and a timing control signal to the pipeline register device 622. 5S A signal group to the first pipeline register device 621, which is composed of a control command to the first controller 611 and a timing control signal to the pipeline register device 621. A group of signals for the 6S bus interface device 4, a group of signals indicating a request for various bus cycle operations to the bus interface device 4, and a bus interface device such as completion of bus operation, busy of the bus interface device, etc. It consists of a signal group indicating the status of.

Next, the operation of the device of the present invention will be described by taking the "block comparison" instruction as an example of the block operation instructions. The "block comparison" sequentially compares the respective data stored in the two "blocks" in the main storage device from the start address of the "block", and the comparison result shows a mismatch or the length of the "block". Is an instruction that terminates execution when either of the conditions for completing the comparison is satisfied.
Therefore, the "block comparison" instruction takes the start address of two "blocks" and the length of the "block" as operands. In the case of this example, all operands need to be stored in the register device 603. The number indicating the block length is set in the counter device 602.
The unit operation of “block comparison” is a comparison for a pair of data in the “block” and is executed as follows.

The first "block" (hereinafter block A
(Referred to as)) to generate the physical address A of the main storage device. Read the data at physical address A. The physical address B of the main memory is generated in order to read the data of the second "block" (hereinafter referred to as block B). The data of the physical address B is read. Make a comparison. If they do not match, the process ends. Count down the number indicating the block length. That is, the contents of the counter device 602 are counted down. If this content is zero, the process ends. Otherwise, return to and repeat the above operation.

FIGS. 2 and 3 show the case of executing this "block comparison" instruction as in the conventional case and the case of using the apparatus of this example, respectively. In these figures, the number n in parentheses indicates each unit operation, and each step from the above to is expressed as follows.

Address A (n) A (n) READ Address B (n) B (n) READ Comparison (n) Count (n)

Further, in FIGS. 2 and 3, the horizontal axis represents time, and the temporal relationship of each step is shown.

In the conventional operation shown in FIG. 2, the address generation and the data reading are pipelined, but this is one of the unit operations. However, since the following relationships cannot be broken, it is impossible to further reduce the time.

Address A (n) needs to be preceded by A (n) READ. The address B (n) needs to be performed prior to B (n) READ. A (n) READ and B (n) READ must be done prior to the comparison (n).

On the other hand, in FIG. 3 showing the operation of this example, the unit operations are carried out in a state where they overlap each other. Looking at each unit operation, the time required for its implementation is
As in the case of FIG. 2 which is not pipelined, the subsequent unit operation is started without waiting for the end of one unit operation. Therefore, the wasteful waiting time of each device is small, and as is clear from a comparison of both figures, 3 unit operations can be realized in the time required for the conventional 2 unit operations.

[0051]

As described above, in the instruction execution device of the integrated circuit microprocessor of the present invention, each unit operation in the "block operation" instruction is pipelined and executed. Therefore, as compared with the conventional instruction execution device, the time required to execute the block operation instruction can be shortened, and the throughput of the entire integrated circuit microprocessor can be improved accordingly.

[Brief description of drawings]

FIG. 1 is a partial configuration diagram showing a configuration of a main part in an integrated circuit microprocessor which is an embodiment of the present invention.

FIG. 2 is an explanatory diagram showing an operation of each part when a “block comparison” instruction is executed by a conventional method.

FIG. 3 is an explanatory diagram showing the operation of each part when a “block comparison” instruction is executed by the device shown in FIG.

[Explanation of symbols]

 1 ... Address Bus 2 ... Control Bus 3 ... Data Bus 4 ... Bus Interface Device 5 ... Internal Address Bus Device 6 ... Instruction Execution Device 601 ... Address Generation Device 602 ... Counter device 603 ... Register device 604 ... ALU device 605 ... First state machine 606 ... Second state machine 607 ... Internal bus device 608 ... Detection device 611 ... 1st control apparatus 612 ... 2nd control apparatus 613 ... 3rd control apparatus 614 ... 4th control apparatus 621 ... 1st pipeline register apparatus 622 ... ..Second pipeline register device 623 ... Third pipeline register device 624 ... Fourth pipeline register device

Claims (1)

[Claims] 1. An instruction decoding unit capable of decoding a block operation instruction having the content of repeatedly executing the same unit operation, and the unit operation constituting a block operation instruction based on a decoding result by the instruction decoding unit. A block operation instruction execution device for an integrated circuit microprocessor, comprising: an instruction execution means that is repeatedly executed by a pipeline method.