JPS60144874A - Vector data processor - Google Patents

Abstract

PURPOSE:To attain an access at a higher speed than a case where the arithmetic result is stored to a main memory by providing the 2nd vector register in addition to the 1st vector register and storing the arithmetic result which is used repetitively to the 2nd vector register. CONSTITUTION:The load data delivered from a main memory 1 is transferred and stored to one of the 1st vector registers 4-1-4-8 via write registers 2-5 and 2-6 and the 1st input selecting circuit 3. While the outputs of operators 6-1-6-4 are also transferred and stored to one of registers 4-1-4-8. The outputs of registers 4-1-4-8 are supplied to operators 6-1-6-4 via read registers 5-1-5-8. With an addition instruction, for example, the addition is designated with an operation code OP. An operand part R1 shows the number of the 1st vector register where the arithmetic result is stored. While an operand part R2 shows the number of the 2nd vector register 14. When the vector data is shifted, the shift is designated with the code OP. Then both parts R1 and R2 designate the numbers of registers which start the shift as well as the store numbers.

Description

[Detailed description of the invention] 〔Technical field〕 The present invention relates to a vector data processing device.

[Prior art]

A conventional vector data processing device is generally configured as follows.

Figure 1 shows a block diagram of a conventional example.

Main memory 1', input selection circuit 2', plural vector registers 3'-1, 3'-2, 3'-8,
Output selection circuit 4', multiple arithmetic units 5'-1, 5'
-2゜5'-3,5'-4 and store register 6'
The load telemeter from the main memory 1' is passed through the input selection circuit 2' to the vector register 3' to which the instruction is specified.
-X, the store data in the vector register 3'-Y specified by the instruction in question passes through the output selection circuit 4', is stored in the store register 6', and then is stored in the main memory 1'
Stored in Further, the data in the vector register 3'-X with the number X specified in the operand part of the instruction is selected by the output selection circuit 4', and
'-2.

On the other hand, the operation result is stored in the vector register 3'-Y specified by the instruction via the input selection circuit 2'.

FIG. 2 is a diagram showing the format of an instruction for the above device, where OP is an operation code, R1 is an operand section that specifies the storage location of the operation result, and R2 is the first operand section that specifies the storage location of the first operand. %R3 is a second operand portion that specifies the storage location of the second operand.

For example, operation code OP specifies addition and R
1 specifies vector register 3'-1, R2 specifies vector register 3'-2, and R3 specifies vector register 3'-3, the contents of vector register 3'-2 and vector register 3'-3 The contents of
The data from the register 3'-2 and the data from the register 3'-3 are then added to the arithmetic unit 5'-1, and the data resulting from these additions is The signals are then stored in the designated vector register 3'-1 via the input selection circuit 2'.

Note that the arithmetic units 5'-1 to 5'-4 represent different arithmetic units; for example, the arithmetic unit 5'-1 is an adder, the arithmetic unit 5'-2 is a multiplier, and the arithmetic unit 5'-3 is a logic unit. Arithmetic unit and arithmetic unit 5'
-4 is chic.

Now, in such conventional examples, generally, due to the limit on the number of vector registers, the result of an operation that will not be used as an operand for the time being is generally stored in the main memory 1', and as a result, when it is used as an operand, it is stored again. The drawback is that it takes a long time to access the data because it has to be read from the main memory and used.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to eliminate the above-mentioned conventional drawbacks, and to provide a means for temporarily saving calculation results depending on the situation and allowing high-speed access when necessary.

[Structure of the invention]

The device of the present invention includes a plurality of first vector registers each holding vector data, and each operand input is fixedly coupled to the output of the first vector register in a one-to-one correspondence to follow an instruction. a store circuit that selects one of the outputs of the first vector register and stores it in the main memory according to an instruction; ``a first input selection circuit that selectively supplies the read vector data to the first vector register;
a plurality of second vector registers each holding vector data; a second input selection circuit that selects one of the output of the arithmetic unit or the output of the first vector register according to an instruction; a write buffer that temporarily stores the output of the second input selection circuit; a selection circuit that selectively supplies the output of the write buffer to the second vector register; and an output selection circuit that selects and supplies vector data to the first input selection circuit.

〔Example〕

Next, the present invention will be described in detail with reference to the drawings.

FIG. 3 is a block diagram showing one embodiment of the present invention.

This embodiment has a main memory 1, a write register 2-1゜2-2.
..., 2-9, first manual selection circuit 3, first vector register 4-1.4-2. ......4 8s read V register 5-1.5-2. ...5-8, arithmetic unit 6-1.6-2゜6-3.6-4, store selection circuit 7,
Strike 779128%0iE2 manual selection circuit 9A, 9B,
Read register 10s m buffer 11, write register 12J! 8 selection circuit 13, second vector register 14,
It has output selection circuits 15-1, 15-2.15-3, and read registers 16-1 and 16-2.16-3.

The operation of this embodiment is as follows.

The load data sent from the main memory 1 is sent via the write register 2-5 or 2-6 and the first manual selection circuit 3 to the first vector register 4-4 of the number specified by the command.
It is transferred and stored in one of 1 to 4-8. In addition, the computing unit 6
The operation results, which are the outputs of -1 to 6-4, are also transferred to the first vector register 4- of the number specified by the instruction via the corresponding write registers 2-1 to 2-4 and the first manual selection circuit 3. 1
~4-8 is transferred and stored.

Also, the first vector register 4 with the number specified by the instruction
The vector data read from -X is selected by the store selection circuit 7 provided before the store register 8, stored in the store register 8, and then stored in the main memory.

On the other hand, as a feature of this embodiment, the outputs of each of the first vector registers 4-1 to 4-8 are transferred to the corresponding successive registers without going through the output selection circuit 4' as in the conventional example shown in FIG. The signals are supplied to the input sides of predetermined arithmetic units 6-1 to 6-4 via terminals 5-1 to 5-8, respectively. In this embodiment, arithmetic units 6-1, 6-2, 6-3 and 6-4
represent an adder, a multiplier, a logic operator, and a shifter, respectively.

The format of the command in this embodiment is as shown in FIG. 4 (5) or
It has the double form shown in Figure (c). When the instruction is in the format shown in FIG. 4(g), for example, an addition instruction specifies addition with the operation code OP, and the first vector registers 4-1 to 4-4 in which the operation result is to be stored in the operand section R.
Specify one register number among -8. By specifying addition with the "Operation" code OP, the first and second operands to be added are forcibly connected to supply input to the arithmetic unit 6-1 (adder). the first vector register 4-1 and the first
When the contents of the vector register 4-2 are determined and this instruction is executed, these contents are sent to the first operand to the arithmetic unit 6-1 (adder) via the read registers 5-1 and 5-2, respectively. and is supplied as the second operand, both are added, and the result of this addition is sent to the first vector register 4-H with the number specified by R via the write register 2-1 and the first manual selection circuit 3. Transferred and stored.

Ru.

Next, if the instruction is in the format shown in FIG. 4 [F]),
For example, in an addition instruction, the operation code OP specifies addition as described above, and R1 is the first
It shows the number of the vector register, and R2 shows the number of the second vector register. The operation in this case is performed as follows.

That is, as described above, the first vector register 4-1
and 4-2, and are supplied to the arithmetic unit 6-1 (adder) via read registers 5-1 and 5-2, respectively, and added here. The first vector register 4-R1 stores the calculation result of the number designated by R through the manual selection circuit 3.

At the same time, the result of this addition is the write register 2-1.
and is selected via the second manual selection circuits 9A and 9B, and is further stored in the write buffer 11 via the read register 10. The write buffer 11 is controlled in a FIFO (first in, first out) manner to match the write timing to the second vector register 14, and the contents of this buffer 11 are transferred via the write register 12 and the selection circuit 13. It is stored in the second vector register 14 with the number specified by R2. Based on the above, in the case of the format shown in Figure 40, the results of operations such as addition are stored in both the first vector register specified by R1 and the second vector register specified by R2. Become.

In the instruction format shown in Figure 40, if R1 is not specified, the operation result is stored only in the second vector register with the number specified by R2, and similarly, if R2 is not specified, it is specified by R1. The operation result is stored only in the numbered oii vector register. In this case, the distinction whether specified or not is made using, for example, the highest bit of the R1 and R2 fields, and if this is 11'', the number of the corresponding vector register is determined by the following bits. , and if it is 0'', it can be distinguished by not specifying it.

Next, when transferring the vector data stored in one of the first vector registers 4-1 to 4-8 to the second vector register 14, use the command format shown in ) in FIG. This operation code OP specifies the transfer from the first vector register to the v2 vector register, and R
1 and R2 respectively designate one number in the first vector registers 4-1 to 4-8 to start transfer and one number in the second vector register 14 to be stored.

This allows the first vector register 4 of the specified number to be
- The contents of R1 are transferred and stored in the second vector register 14 at the specified number via the second manual selection circuit 9B, read register 10, write buffer 11, write V dimeta 12, and selection circuit 13. Ru.

Next, when transferring the vector data stored in one of the second vector registers 14 to one of the first vector registers 4-1 to 4-8, the fourth
A transport instruction having the instruction format of FIG. 0 is used. That is, the operation code OP specifies that the transfer is from the second vector register to the first vector register, and R1 and R2 respectively specify the first vector registers 4-1 to 4-4 to store the transferred vector data. Specify the number of one vector register in -8 and the number of one vector register in the second vector register 14 to start the transfer. As a result, the contents of the R2#th second vector register 14 specified by the output selection circuit 15-1
~15-3 (this is selected by one of circuit 1
5-1), is supplied to the first manual selection circuit 3 via the corresponding read register 16-1 and write register 2-7, and is supplied to the first vector register 4 with the number R1 designated via the circuit 3. - Stored in R1. In this embodiment, the output selection circuits 15-1 to 15-3. and corresponding successive registers 16-1 to 16-3. Three circuits of write registers 2-7 to 2-9 and corresponding inputs of the first manual selection circuit 3 are provided.
The above transfer instructions can be processed in parallel for three instructions.

As described above, according to the present embodiment, the vector calculation process that is generally performed, that is, the calculation process of reading vector data from the main memory 1, performing a specified calculation, and storing the result in the main memory 1 again, is performed. Instead, by providing a second vector register 14 made up of a plurality of vector registers, the shadow calculation results that are used repeatedly can be stored in the main memory 1 by storing them in the second vector register 14. In addition, if the operation result does not need to be used immediately as an operand for the next instruction, by saving the operation result to the second vector register 14, the operation result can be accessed at high speed. It is possible to effectively utilize the first vector registers 4-1 to 4-8, of which there are only a few.

Furthermore, according to the configuration of this embodiment, since the connections between the first vector registers 4-1 to 4-8 and the arithmetic units 6-1 to 6-4 are fixed, the command for specifying the arithmetic operation is The first and second operands are automatically determined by simply specifying the operation code OP in , so there is no need to specifically specify them. The instruction format is simpler than in the example, and the related hardware can be simplified accordingly.

The above shows one embodiment of the present invention, and the present invention is not limited thereto.

For example, in the case of a single leprosy, the number of arithmetic units 6-1 to 6-4 is four, and therefore the ml vector registers 4-1 to 4
Although the number of −8 is set to eight, this is only an example, and the number of these γL and the type of arithmetic unit can be appropriately set depending on the required operating environment.

Furthermore, it is clear that the various successive registers and write registers shown in this embodiment can be included on the output side or input side of adjacent circuits, thereby eliminating the need for special provision of these registers. .

Further, in this embodiment, although the number of vector registers in the second vector register 14 is not specified,
This may also be set to an appropriate number depending on the required operating environment.

Further, the command format shown in Figure 4 (@) is only an example and is not limited to this.

Also, in Fig. 3, the second manual selection circuit is divided into 9A and 98, but this division was done to avoid complication of the drawing, and there is no particular need for division in the actual circuit. it is obvious.

〔Effect of the invention〕

As described above, when used in the present invention, by providing a second vector register in addition to the first vector register, the main If you store it in memory, you can access it at high speed, and if you do not need to use the operation result immediately as an operand for the next instruction, you can save the operation result to this second vector register. By doing so, it is possible to effectively utilize the first vector register, of which there is only a limited number.

Furthermore, according to the configuration of the present invention, the format of the instructions is simple, and the related software can be simplified accordingly.

[Brief explanation of the drawing]

FIG. 1 is a block diagram for explaining the conventional example, FIG. 2 is a diagram for explaining the instruction format of the conventional example, FIG. 3 is a block diagram showing an embodiment of the present invention, and FIG. ) and FIG. 4 are diagrams for explaining the format of the non-execution tl'r command. In the diagram, 1... Main memo 1c 2-1 to 2-9.12...
...Write register, 3...First manual selection circuit, 4-1 to 4-8...@1 vector register,
5-1 to 5-8. 10.16-1 to 16-3...
... Successive register, 6-1 to 6-4 ... Arithmetic unit, 7 ... Store selection circuit, 8 ... Store register, 9A, □B ...・Second selection circuit, 1
1... Graduation buffer 7, j3... Selection circuit, 14... Second vector register, 15-1
~15-3... Output selection circuit. 4th Insect No. 4

Claims (1)

[Scope of Claims] A plurality of first vector registers each holding vector data, each operand input having a one-to-one correspondence with the output of the first vector register and fixedly coupled to the output according to an instruction. a store circuit that selects one of the outputs of the first vector register and stores it in the main memory according to an instruction; a first input selection circuit that selects and supplies vector data sequentially output from the first vector register to the first vector register; a plurality of second vector registers each holding vector data; and a plurality of second vector registers each holding vector data; or one of the outputs of the first vector register; a write buffer that stores the output of the second input selection circuit; and a write buffer that stores the output of the second input selection circuit; and an output selection circuit that selects and supplies vector data read from the second vector register to the first input selection circuit according to an instruction. vector data processing device.