JPS6058487B2 - data processing equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a data processing device having an arithmetic function between registers, and more specifically, to a data processing device that can perform arithmetic operations between registers that cannot be read simultaneously at high speed. It is.

An IC element called a so-called file register is sometimes used as a general-purpose register in a data processing device, but in general, this type of IC cannot read all bits at the same time, but only some addressed bits can be read at the same time. I'm getting ready to release it.

FIG. 1 shows an example of a conventional configuration for performing arithmetic processing between registers in a data processing device using such an IC as a general-purpose register. In Figure 1, 1 is an operation register for setting an instruction, and 1a is the first operation register.
The operation field lb indicates the second operation field. 2 is a selector that selects the first operation field and the second operation field; 3 is a register group in which operations are performed; 4 is a register that temporarily stores the contents of the first operand; and 5 is an arithmetic unit.

When performing an operation on register R1 of the first operand and register R2 of the second operand, R
1 and R2 cannot be read, so selector 2 selects the first operation, field 1a, and sends it to register group 3, which uses this as an address to read the first operand R1 and set it in register 4. . At the next timing, the selector 2 selects the second operation field lb, and the register 3 sends the contents of the second operand R2 to the arithmetic unit 5. In this way, the contents of the first and second operands are input to the arithmetic unit 5, and the arithmetic operation instructed by the operation register 1 is performed. The result of the operation is stored in register R1 or R2 of register group 3 at the next timing. A time chart of this operation is shown in FIG. By the way, a drawback of FIG. 1 is that since the first and second operands are read out separately, it takes a long time to complete the operation.

Therefore, in order to shorten this operation processing time, there is a method in which each register in the register group is made completely independent, and two selectors are used to simultaneously select and operate the first and second operands. Figure 3 shows its block diagram, where 6 is a completely independent register group, 7a and 7
b are independently indicated by a first operation field 1a1 and a second operation field 1b.
This is a selector that selects l and R2 from the register group 6.
Note that 8 indicates a selector for writing the calculation result. However, a completely independent register group is generally more costly than a filed register group, and is not suitable for a data processing device that uses a large number of registers. Furthermore, by dividing the register group 3 in Figure 1 into two and distributing and managing the first and second operands in each of the divided register groups, direct operation of the two operands is possible. However, managing the distribution of operands is a considerable burden on programmers, and complete distribution is impossible in general programs.

SUMMARY OF THE INVENTION An object of the present invention is to eliminate the problems of the prior art as described above, and to provide a data processing device with short calculation processing time and low cost. Therefore, a feature of the present invention is that the same register is provided twice in the file format, and two operands can be read simultaneously by selecting them in the first and second operation fields. It is.

FIG. 4 is a block diagram of an embodiment of the present invention. In the figure, 3a and 3b are first and second register groups using a file register IC, and these register groups are each independently selected and their contents are read out. The operation register 1, selector 2, and arithmetic unit 5 are the same as those in FIG. Now, the register groups 3a and 3b are duplicated, and the same contents are written in the same locations of 3a and 3b.

Therefore, field 1a of operation register 1,
The register R1 of the first operand indicated by 1b and the second
When performing an operation on the operand register R2, the information in the first operation field 1a is sent to the first register group 3a through the selector 2, and the first register group 3a uses this as an address to read out the first operand R1 and send it to the arithmetic unit 5. send to Similarly, the information in the second operation field 1b is sent directly to the second register group 3b, and the second register group 3b uses this as an address to read out the second operand R2 and send it to the arithmetic unit 5. This operation is performed in parallel. The arithmetic unit 5 is operated by the operation register 1.
The operation instructed by is performed, and the result of the operation is stored in the register at the same location in both the first and second register groups 3a and 3b at the next timing.
Since it is assumed to be stored in the operand register R2,
When storing the address information in the first register group 3a, the selector 2 switches the address information to the information in the second operation field 1b. A time chart of this operation is shown in FIG. In addition, in FIG. 4, the first and second register groups 3a and 3b use file registers C, but they may be register groups of other types, or they may be used to store the results of operations. is stored in the register R1 of the first operand, the selector 2 may be provided on the second register group 3b side.

With the configuration described above, the present invention can achieve the following effects.

(1) Since the first operand and the second operand can be read simultaneously, it is possible to realize a short arithmetic processing time equivalent to a method using completely independent register groups.

(2) In general, even if a group of registered registers is twice as large, it is easier to lower the cost than a group of registers that are completely independent, and it is cheaper than a system that uses a group of registers that are completely independent. Cost can be lowered.

(3) Due to (1) and (2) above, the calculation processing time is shortened.
Moreover, a low-cost data processing device can be realized. (4
) It is possible to perform direct operations between any two operands without distributing and managing the operands.
Programmers and grammarians are completely freed from operand distributed management.

[Brief explanation of the drawing]

FIG. 1 is a bookmark diagram of the part according to the present invention of a conventional data processing device having one filed register group, FIG. 2 is a time chart for explaining the operation of FIG. 1, and FIG. FIG. 3 is a block diagram of a portion of a conventional data processing device having completely independent register groups according to the present invention, FIG. 4 is a block diagram showing an embodiment of the present invention, and FIG. FIG. 2 is a time chart for explaining the operation of FIG. 1...Operation register, 1a...
...First operation field, 1b...
・Second operation ●Field, 2... Selector, 3a... First register group, 3b...
・Second register group, 5... Arithmetic unit.

Claims (1)

[Scope of Claims] 1. A data processing device having a function of performing an operation between a register specified by a first operation field of an instruction word and a register specified by a second operation field, Duplicate register groups with the same configuration are provided, and the same operands are stored twice in both of the duplicated register groups, and when reading the operands, the first and second operations are performed independently. A data processing device characterized in that the contents of the registers specified by each field are simultaneously read from the double register group when performing an operation between the registers. 2. The data processing device according to claim 1, wherein each register group is composed of a file register IC.