JPH02240734A - Information processor - Google Patents

Abstract

PURPOSE:To shorten the executing time for an inter-register exchange instruction by using a means holding the information showing which one is valid in two duplex registers, a control means which refers to or updates the holding means, and a register which bypasses a main arithmetic circuit to receive data. CONSTITUTION:A read control circuit 14 refers to a valid/invalid information storage 13 and makes the operand registers 2 and 3 read the contents of a valid register with control of selectors 9 and 10. Then one of two data is written into an output register 5 via an arithmetic circuit 4, and the other data is written into a register 6 after bypassing the circuit 4. A write control circuit 12 controls the selectors 7 and 8 and assigns the contents of both registers 5 and 6 to the register files 1-1 and 1-2 one by one while having an access to the storage 13. As a result, the writing cycle is shortened for an inter-register exchange instruction.

Description

[Detailed description of the invention]

[Industrial Application Field] The present invention relates to an information processing device having a register exchange instruction. [Prior Art] Conventionally, in an information processing device that employs a pipeline mechanism, when there is only one general-purpose register group (register file), register exchange instructions (for example, EXG AO
, BOc7), '>, an instruction to swap the data in registers AO and BO) requires IT to write to the register, even if register reading can be done using IT (T: machine cycle). , which required at least 2T. FIG. 3 is a block diagram of an example of a conventional information processing device. For the sake of simplicity, the information processing device shown in FIG. 3 is comprised of a register file 1, an operand register 2, an operand register 3, an arithmetic circuit 4, an output register 5, and a control circuit 15, which are the minimum necessary functional blocks. Register file 1 has one system of write addresses and two systems of read addresses.
The operation is such that writing to a register indicated by a write address and reading from two registers indicated by two different read addresses can be performed simultaneously. Now, consider the execution cycle of an inter-register exchange instruction. The data of the two target registers from the register file 1 is simultaneously output to the operand register 2.3.0 In the 0-order IT, the contents of one of the registers is strobed to the output register 5 through the arithmetic circuit 4.0 Writing to register file 1 begins from the next IT. In other words, in the next IT, the data currently being strobed in the output register 5 is written to the target register in the register file 1, and at the same time, the data in the other operand register is strobed to the output register 5 through the arithmetic circuit 4. be done. Furthermore, the data in the output register 5 is written to the target register in the next IT. FIG. 4 is a time chart of execution of the above-mentioned register exchange instruction. As can be seen from Figure 0, in which the number of stages of the pipeline is five, when there is one register for outputting the operation result, P4, which is a write cycle, is executed twice.

[Problem to be Solved by the Invention J] The conventional information processing device described above requires two cycles for writing when executing an inter-register exchange instruction, which causes pipeline disturbances, especially in a pipeline-controlled processing device. There are drawbacks. An object of the present invention is to provide an information processing device that takes a short time to execute a register exchange instruction. [Means for Solving the Problems] The information processing device of the present invention has one system of write addresses and two systems of read addresses, and has one system of write addresses and two systems of read addresses. The first register with the same configuration can read data from two registers at the same time. a second register file; a first selection means for selecting a first output of the first register file or a first output of the second register file; a second selection means for selecting a second output of the register file of the first register file; The first . a second register; an arithmetic circuit that receives the contents of the first and second registers as input; a third register that holds the calculation results of the arithmetic circuit; and a third register that holds the contents of the first register or the second register. a third selection means for selecting; a fourth register for holding the output of the third selection means; and selection of the output of the third register or the fourth register;
a fourth selection means for outputting to the first register file; and selecting the output of the third register or the fourth register;
a fifth selection means for outputting to the second register file; and a fifth selection means for controlling the fourth and fifth selection means and the first and second register files; write control means having a function of allocating one of the contents of the four registers to a first register file and allocating the other to a second register file for writing; and the first register file or the second register file. When data is written to the register file, the contents of the target register in the register file to which the data was written are made valid, and the contents of the same register as the target register in the other register file are stored as invalid until updated thereafter. control the valid/invalid information storage means, the first and second selection means, and the first and second register files; and read control means for reading valid data from the registers of the register file. [Operation] The contents of the register targeted by the register exchange instruction are the third and fourth registers.
Also, the register files are duplicated, and the contents of the third and fourth registers are written to one register file in the same cycle and the other to the second register file in the same cycle. written. That is,
The write cycle for the register exchange command is completed by IT, and the overall time is reduced compared to the conventional IT method. [Example 1] Next, an example of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram of an information processing apparatus showing an embodiment of the present invention, and FIG. 2 is a time chart showing the operation of an inter-register exchange instruction in the embodiment of FIG. Register files 1-1 and 1-2 are a collection of general-purpose registers, etc., and are duplicated here. Registers 2 and 3 are operand registers. The arithmetic circuit 4 is a unit that receives the contents of the operand registers 2 and 3 as input and executes arithmetic operations or logical operations. The output register 5 is a register for receiving the calculation result of the calculation circuit 4. Register 6 transfers the contents of operand register 2 or 3 to arithmetic circuit 4.
Bypass and receive. Also, units 7.8, 9.1
0 and 11 are two-man selectors. The valid/invalid information storage device 13 maintains the consistency of the duplicated registers when writing is performed to any register.
This is for holding information as to which data among the duplicated registers is valid at that time. When writing the contents of two registers in an inter-register exchange instruction, the write control circuit 12 allocates one register to each arbitrary register in the duplicated register files 1-1 and 1-2. It has a writing function. The read control circuit 14 has a function of reading valid data by referring to the valid/invalid information storage device 13 when reading any register. Next, the operation of the inter-register exchange instruction in the embodiment shown in FIG. 1 will be explained with reference to FIG. It is assumed here that each instruction step is executed in a pipeline. First, as the first step, the register read operation will be explained. The read control circuit 14 refers to the valid/invalid information storage device 13 to read the contents of any register that is the target of an inter-register exchange instruction (hereinafter simply referred to as an instruction).
Selectors 9 and 1o select the contents of valid registers, respectively.
is read into operand registers 2 and 3. Subsequently, in the next step, one data passes through the arithmetic circuit 4 and is written to the output register 5, and the other data bypasses the arithmetic circuit 4, that is, passes through the selector 11 and is written to the register 6. In this case, the write control circuit 12 controls the selectors 7 and 8, and while accessing the valid/invalid information storage device 13, writes the contents of the output register 5 and register 6 one by one to the register files 1-1 and 1-. A write operation is performed by assigning it to 2. At this time, in the valid/invalid information storage device 13, of the duplicated registers, it is assumed that the contents of the register to which the write operation was actually performed are valid,
The validity information in the register, which states that the contents of the other register are invalid until a subsequent write operation is performed, is rewritten, and an action is taken to hold this. The above operation is shown in a time chart as shown in FIG. 2. It can be seen that compared to the case of FIG. 4, the write cycle of the inter-register exchange instruction is completed in IT, and the IT time is shortened as a whole. [Effects of the Invention] As explained above, the present invention provides means for duplicating register files and retaining information as to which of the duplicated registers is valid and which is invalid, and referring to the retaining means. Alternatively, by having a control means for updating and a register or the like that receives data by bypassing the main arithmetic circuit, there is an effect that the execution time of the register exchange instruction can be shortened.

[Brief explanation of drawings]

FIG. 1 is a block diagram of the main parts of an information processing device showing an embodiment of the present invention, FIG. 2 is a diagram schematically showing the pipeline operation of this embodiment, and FIG. 3 is a conventional information processing device. FIG. 4 is a block diagram of the main parts of the conventional vibration line operation shown in FIG. 3. 1-1.1-2...Register file, 2.3...
・・Operand register, 4・ ・ ・ ・ ・ ・
・ ・ Arithmetic circuit, 5 ・ ・ ・
・ ・ ・ ・ Output register, 6... Bypass register, 7, 8.9
．． 10.11... Selector, 12... Write control circuit, 13... Valid/invalid information storage device, 14... Read control circuit.

Claims (1)

[Scope of Claims] 1. An information processing device having a register exchange instruction, which has one system of write addresses and two systems of read addresses, and is indicated by a write address, and a write to a register is indicated by two different read addresses. First and second register files with the same configuration that can read from two registers simultaneously; and a first register file that selects the first output of the first register file or the first output of the second register file. a second selection means for selecting a second output of the first register file or a second output of the second register file; and an output selected by the first and second selection means. an arithmetic circuit that receives the contents of the first and second registers as input, a third register that holds the arithmetic result of the arithmetic circuit, and a first register or a third selection means for selecting the contents of the second register; a fourth register for holding the output of the third selection means; and selection of the output of the third register or the fourth register;
a fourth selection means for outputting to the first register file; and selecting the output of the third register or the fourth register;
a fifth selection means for outputting to the second register file; and a fifth selection means for controlling the fourth and fifth selection means and the first and second register files; write control means having a function of allocating one of the contents of the four registers to a first register file and allocating the other to a second register file for writing; and the first register file or the second register file. When data is written to the register file, information is stored that makes the contents of the target register in the register file written valid, and invalidates the contents of the same register as the target register in the other register file until it is updated thereafter. control the first and second selection means and the first and second register files; 1. An information processing apparatus comprising: read control means for reading valid data from a register of a register file.