JPS63188230A - Information processor - Google Patents

Abstract

PURPOSE:To eliminate the need of a register file exclusive for an address generating circuit and to shorten a machine cycle by sharing a 4-port register file for both production of addresses of an address generating circuit and arithmetic processing of an arithmetic and logic unit (ALU). CONSTITUTION:A 4-port register file 100 contains three read-only ports 11, 21 and 31 which fetch successively two register values showing the source data and a single register value showing the address data as well as a write-only port 41 which writes the value showing the destination data obtained by an ALU300 into an exclusive register at every write enable state set in the timing synchronous with a microinstruction. An address generating circuit 200 decodes the register value at every fetching and produces addresses. In such a constitution, no special register file is needed for the circuit 200 and both reading and writing jobs are carried out in parallel with each other. Then the machine cycle is shortened.

Description

Detailed Description of the Invention (Industrial Application Field) The present invention relates to an information processing device that performs arithmetic processing using a three-bus type operator unit (ALIJ), and in particular to an improvement in the hardware configuration of register level architecture. Regarding.

(Prior Art) In recent years, with the advancement of VLSI technology, pipeline processing has been performed even in one-deep computers, and various attempts have been made to speed up processing at the instruction processing level or instruction word processing level.

However, when attempting to construct an information processing apparatus that allows a single-chip computer to perform predetermined information processing, conflicting accesses to register files often occur.

For example, in the information processing device of this scale, when generating operand addresses and branch destination addresses by the address generation circuit, the index register and pace register are referred to, and those registers are used as the source data of the ALU. Read the register file in which the value of is stored.

In particular, in information processing equipment that performs arithmetic processing using a three-bus ALU, two source data and one destination data are required, so the register file can be accessed four times in one machine cycle. will be required.

However, when a two-port register file is used as in the past, one port is shared for reading and writing. Therefore, half of one machine cycle is the read time, and half of that is the write time, so if there is contention in access to the register file as described above, it becomes difficult to shorten the machine cycle.

Furthermore, a configuration has been proposed in which a 3-port register file is used in which 2 ports can be read and 1 port can be written. However, even in this case, there is no port for address generation in the register file, so a copy of the register file must be prepared exclusively for the atray generation circuit.

(Problems to be Solved by the Invention) As described above, in the conventional three-bus configuration information processing device, it is difficult to shorten the machine cycle when using a two-port register file. Ta. Further, even if a 3-port register file is used, it is necessary to have duplicate register files, so there is a problem that the hardware configuration of the register level architecture becomes complicated.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide an information processing apparatus that can cope with competing accesses and eliminates the need to copy a register file.

[Structure of the Invention] (Means for Solving the Problems) In order to achieve the above object, the present invention provides an information processing device with a three-bus configuration, in which 12 register values representing source data and one register value representing address data are used. Three read-only ports that read register values sequentially, and ALU
A 4-port register file with one write-only port for writing a value indicating destination data into a dedicated register, and each time a register value indicating address data stored in this 4-port register file is sequentially retrieved, The present invention is characterized by comprising an address generation circuit that sequentially decodes the register values to generate addresses.

(Function) As described above, since a 4-port register file is used in the present invention, this 4-port register file is shared for address generation in the address generation circuit and for arithmetic processing in the ALU. , it is possible to execute the processing of B in parallel.

(Embodiment) FIG. 1 is a block diagram showing an outline of essential parts of an embodiment of an information processing apparatus to which the present invention is applied.

In this embodiment, a 4-port register file 1
According to the file contents of 00, the address generation circuit 200
The 4-port register 100 is configured so that each process in the 3-bus type ALU 300 is executed.

That is, the 4-port register file 100 has B ports 11 . A bow 1-21. A C port 31 is provided, and a D port 41 is provided as a write-only port.

Then, from the A port 21, the register number of the index register 20 that holds the register number indicating address data is taken in, and
From the port 31, the pace register 10 and the register number of the pace register 30, which respectively hold register numbers indicating source data, are taken in.

Further, the D port 41 writes the contents of the destination data by the ALLI 300 to the register 40.

On the other hand, the address generation circuit 200 sequentially takes in the A port data stored in the 4-port register file 100 as read data 101, and sequentially decodes the Δ port data to generate an address.

In addition, the ALU 300 has a 4-port register file 10
Every time the C port data and C port data stored in C port data 0 are read out to the corresponding source data bus (source bus A) 301 and source data bus (source bus B) 302 as read data 102 and 103, respectively, the C Arithmetic processing is executed based on the port data and C port data, and the data obtained by this processing is sent to the destination bus 300.

In addition, in the figure, 104 is a 4-port register file 100.
105 indicates a write enable signal.

Next, the operation of this embodiment will be explained as follows.
The instructions prefetched by the pipeline processor are decoded by the address generation circuit 200. At that time, if the value of the index register is required, please refer to the 4-port register value. When the A port data stored in the file 100 is retrieved as read data 101, the address generation circuit 200 decodes the contents of the A port data and performs address calculation to generate an address.

Then, the instructions already in the arithmetic stage during the same cycle in which the address is generated are required for execution, and the port data and C port data are sent from the 4-port register file 100 to the source data bus 301, respectively.
When the data is read out in the ALU 300, it is extracted based on the C port data and the C port data.

The register numbers at this time are pace register 10 and pace register 3.
It is held at 0, and the value specified in the predetermined field of the instruction is entered as this value.

On the other hand, the 4-port register file 100 contains
An enable signal is added at the timing when the instruction is decoded by means not shown. At this timing, the destination data of ALU300 is transferred to destination bus 3.
It is added to the 4-port register file 100 as m write data 104 via 03.

Then, D port 4 of the 4-port register file 100
1 to destination data is not indicated and the value is register 4
Written to 0. The value of this register 40 is the same value as either register 10 or register 30 when the two-operand method is applied.

In this way, if each process in the address generation circuit 200 and ALLI 300 is performed using the 4-port register file 100, there is no need to provide a separate register file exclusively for the address generation circuit 200, and reading and writing in one machine cycle can be performed. Machine cycles can be easily shortened because they can be performed in parallel.

[Effects of the Invention] As explained above, in the information processing device to which the present invention is applied, the address generation circuit can generate addresses according to the file contents of the 4-port register file, so a separate dedicated address generation circuit is required. There is no need to provide a register file, and the machine cycle can be easily shortened.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an outline of essential parts of an embodiment of an information processing apparatus to which the present invention is applied. 100... 4-port register file 200... Address generation circuit

Claims (1)

[Claims] (1) In an information processing device that performs arithmetic processing using a three-bus arithmetic unit (ALU), three read-only ports that sequentially import two register values indicating source data and one register value indicating address data. and one write-only port that writes a value indicating destination data by the ALU to a dedicated register each time the write is enabled in synchronization with a microinstruction; 1. An information processing device comprising: an address generation circuit that generates an address by sequentially decoding contents indicated by a register value each time a register value indicating address data stored in the address data is sequentially retrieved.