JPH01231126A - Information processor - Google Patents

Abstract

PURPOSE: To decrease the waiting time by using the write data concerned instead of read-out data of the instruction concerned, when a write address of a preceding instruction and a read-out address of the instruction concerned coincide, at the time of executing a pipeline processing.

CONSTITUTION: In an I stage, an instruction reading-out circuit 2 reads out an instruction to an instruction register 6 of an arithmetic circuit 1 from a cache memory 4 or a main storage device 5. In an R stage, by a rise of a clock passing through an AND gate AND, each instruction OP, D, S₀ and S₁ is set to the instruction register 6, and by register read-out addresses S₀, S₁, the contents of a register file 12 are read out to buses L₀, L₁. Simultaneously, addresses S₀, S₁ are set to a register interference detecting circuit 8, an instruction code OP is set to an instruction decoder 7, and a result of decoding by the instruction decoder 7 is set to the register interference detecting circuit 8. If an interference is generated, read-out of the instruction register is stopped, and unless the interference exists, if the preceding write address and the read-out address concerned coincide, write data is used as read-out data.

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