JPS61292741A - General-purpose register - Google Patents

Abstract

PURPOSE:To shorten the reading time in an inter-register arithmetic mode by reading a storage cell of P columns and n*m rows through plural row selection circuits at a time. CONSTITUTION:The 1st register selection circuit 2-13 selects the 8-bit information equivalent to a register out of eight 8-bit general-purpose registers included in the 1st register strings 2-4, for example, selected previously by the 1st register selection signal 2-12. This selected information is outputted to an input/output buffer 2-14. At the same time, the 2nd register selection circuit 2-16 selects the 8-bit information equivalent to a register in response to the state of the 2nd register selection signal and outputs it to an output driver 2-17. These information of the buffer 2-14 and the driver 2-17 are outputted onto the 1st and 2nd data buses 1-5 and 1-6 under the control of the 1st and 2nd read signals 2-9 and 2-10 respectively.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a storage means that can be referenced at high speed in an information processing device integrated on a single semiconductor chip, and particularly to a general-purpose register in a central processing unit.

(Prior Art) Information processing devices generally have general-purpose registers for temporarily holding processing data. These general-purpose registers are made up of a group of multiple registers that can be used by programs, and can also be accessed from the main memory at higher speeds.

Even in information processing devices (single-chip microcombiners) that integrate various circuits such as general-purpose registers, arithmetic circuits, and various control signal generation circuits for controlling these on a single semiconductor chip, General-purpose registers are used for similar purposes, and in recent years there has been an increasing demand for improved processing performance by increasing the capacity of general-purpose registers and increasing the speed of switching between program execution environments.

The structure of a general-purpose register conventionally used in an information processing device will be explained with reference to FIG.

The central processing unit (hereinafter referred to as CPU) 4 has general-purpose registers 4-2. Arithmetic logic circuit (hereinafter referred to as ALU) 4
-3. Timing control circuit 4-4. Data bus 4-5.
First temporary register 4-6. It includes a second temporary register 4-7 and an ALU latch 4-8.

General-purpose register 4-2 is connected to AL via data bus 4-5.
It exchanges data with the outside of U4-3 and CPU4. First temporary register 4-6. The second tempo 2 reregister 4-7 is a register that temporarily holds data to be calculated by the ALU 4-3, and is a register that temporarily holds data to be operated on the ALU 4-3.
5-bit data is written and output to ALU 4-3. The ALU latch 4-8 is a latch that temporarily holds the operation result of the ALU 4-3, and its contents are stored on the data bus 4-5.
is output above.

Next, the operation of the inter-register arithmetic operation of the CPU 4 will be explained with reference to the timing diagram of FIG.

During the period T1, one of the operation data from the general-purpose register 4-2 is output onto the data bus 4-5, and written to the first temporary register 4-6 in synchronization with the timing tl. Next, during the period T2, the other operation data is output from the general-purpose register 4-2 onto the data bus 4-5, and written to the second temporary register 4-7 in synchronization with the timing tl. ALU synchronized with the same tl timing
4-3 starts the arithmetic and logic operation and sends the result of the operation to t3.
The calculation result is written to the ALU latch 4-8 in sync with
4 is written to general-purpose register 4-2.

Also, if an interrupt or task switching occurs,
Software processing temporarily saves the processed data in the register to the main memory, and then transfers the register information necessary for interrupt processing and new task processing to the general-purpose register.

(Problems to be Solved by the Present Invention) As explained above, in the conventionally used general-purpose registers, when performing an operation between registers, two pieces of operation data must be read out at two separate timings. It has the major drawback of reducing processing time. In addition, when switching the program execution environment due to an interrupt or other factors, the contents of general-purpose registers are temporarily saved to main memory, and the general-purpose register information is read from main memory in order to set the new execution environment. It also has disadvantages in that it requires software processing to store data in a general-purpose register and requires a large amount of switching time.

(Means for Solving the Problems) The general-purpose register of the present invention is an information processing system that integrates a general-purpose register and an arithmetic unit on a single semiconductor chip, which has p register sets each consisting of n m-bit registers. The device includes a column selection circuit, a plurality of row selection circuits, and a memory cell, the memory cell has a structure of p columns and n-+m rows, and the column selection circuit selects one column from among the p columns; Subsequently, a plurality of row selection circuits independently select data in a plurality of sets of m-bit registers from n+m bits, and output the selected data to the arithmetic circuit.

(Example) Next, the present invention will be explained with reference to the drawings.

FIG. 1 shows a CPU having general-purpose registers based on the present invention.
FIG. 2 is a block diagram of one embodiment of the invention.

CPUI has improved general purpose registers 1-2゜ALLI
I-3, timing control circuit 1-4. First data bus 1-5, second data bus 1-6, first temporary register 1-7. It includes a second temporary register 1-7 and an ALU latch 1-9.

General register 1-2 has register set selection signal 1-1.
0 is input as a control signal. This general-purpose register 1-
2 exchanges data with the ALUI-3 and the outside of the CPUt via the first data bus 1-5, and at the same time outputs the calculated data onto the second data bus 1-6. do. First temporary register 1-7. The second temporary register 1-8 is a register that temporarily holds data to be operated on in ALLI 1-3, and under the control of the timing control circuit 1-4, the first temporary register 1-7 stores the first data. Arithmetic data is written to the bus 1-5 and the second temporary register 1-8 from the second data bus 1-6, respectively, and output to the ALU 1-3. A
LU latch 1-9 is a latch that temporarily holds the operation result of ALUI-3, and its contents h% first data bus 1-
5 is output.

Next, a more detailed circuit configuration of the general-purpose register 1-2 will be explained with reference to FIG. Here, as an example, eight 8-bit general-purpose registers can be selected by register set selection signals 1-10, respectively.

In the memory cell section 2-I, a 1-bit memory cell 2-2
Eight memory cells having the same configuration are arranged vertically to form the first 8-bit register 2-3. Eight registers with the same configuration as this first 8-bit register 2-3 are arranged vertically.
A first register column 2-4 is constituted by 64 bit storage cells.

In the memory cell section 2-1, there are a total of 8 columns having the same configuration as the first register column 2-4 consisting of 64 bits, 64 bits in the vertical direction and 8 columns in the horizontal direction. Although it has an elongated structure, in this embodiment, for the purpose of eliminating redundancy in the drawings, we focused on the first 8-bit register 2-3, and the details of the other registers in Fig. 2 are omitted. The illustration is omitted.

The column selection circuit 2-5 receives the register set selection signal 1-10.
One of the eight column selection signals is activated depending on the state of the column selection signals 2 to 6. In this embodiment, a case will be explained in which the column selection signals 2-6 are activated.

The control gate 2-7 receives the first read signal 2-9° and the second read signal 2-9.
Read signal 2-10. Under the control of the write signal 2-11, the column selection signal 2-6 is transmitted to the memory cell, and the first register column 2-6 including eight 8-bit general-purpose registers corresponding to the vertical direction of the memory cell section 2-1 is transmitted. 4, a total of 64 bits are selected at once.

The first register designation signal 2-12[, generated by the register designation field of the instruction code or the timing control circuit 1-4, is input to the first register selection circuit 2-13. The first register selection circuit 2-13 corresponds to a register from among eight 8-bit general-purpose registers, a total of 64 bits, which are previously selected according to the state of the first register designation signal 2-12. Select 8-bit information.

The input/output buffer 2-14 receives the first read signal 2-9.
Under the control of , the register information selected by the first register selection circuit 2-13 is output onto the first data bus 1-5. In addition, input/output buffer 2-14h, write signal 2-
11, write data on the first data bus 1-5 is supplied to and written into the memory cell section 2-1 via the first register selection circuit 2-13.

Like the first register selection circuit 2-13, the second register designation signal 2-15 is generated by the register designation field of the instruction code or the timing control circuit 1-4, and is sent to the second register selection circuit 2-16. input. The second register selection circuit 2-16 receives a second register designation signal 2-15.
Independently of the first register selection circuit 2-13, 8-bit information corresponding to l registers is selected from a total of 64 bits of the eight 8-bit general-purpose registers that are previously selected according to the state of the register. select.

The output driver 2-17 outputs a second read signal 2-10.
Under the control of , the register information selected by the second register selection circuit 2-16 is output onto the second data bus 1-6.

Next, the operation of reading data from the general-purpose register 1-2 will be explained with reference to the same FIG.

In this embodiment, it is assumed that the column selection signal 2-6 is already active due to the register set selection signal 1-10, and the 64 bits in the vertical direction of the first register column 2-4 are in the selected state. When the first read signal 2-9 or the second read signal 2-10 becomes active, the control gate 2-7 reads the first register string 2-9 corresponding to eight 8-bit registers. 4, a total of 64 bits of data, are selected and output on data line 2-18. Subsequently, the first register selection circuit 2-13 and the second register selection circuit 2-16 select the data on the first data bus 1-5 and the second data bus 1-.
The data to be output on 6 is selected at the same timing,
The output buffers 2-14 are output to the first data bus 1-5 and the second data bus 1-6 via the output driver 2-17, respectively. That is, the first register selection circuit 2-13 selects the first register column 2-4 selected first based on the state of the first register selection signal 2-12.
Eight 8-bit general-purpose registers included.

8 bits of information corresponding to the register is selected from a total of 64 bits and output to the human output buffer 2-14.

At the same time, the second register selection circuit 2-16 also selects 8-bit information corresponding to registers, independently of the first register selection circuit 2-13, according to the state of the second register selection signal 2-15. Select and output to the output driver 2-17. The human output buffer 2-14 receives the first read signal 2-
9, the register information selected by the first register selection circuit 2-13 is transferred onto the first data bus 1-5, and the output driver 2-17 outputs the second read signal 2-13.
Under the control of 1O, the register information selected by the second register selection circuit 2-16 is output onto the second data bus 1-6, respectively.

Through the above processing, 92 register information can be read at the same timing.

Further, in FIG. 2, during a write operation, data to be written is placed on the first data bus 1-5. At this time, the first register selection circuit 2-13L1 selects one of the eight 8-bit general-purpose registers previously selected based on the state of the first register designation signal 2-12, corresponding to the register from a total of 64 bits. The write data line 2-19 is set to a selected state. The input/output buffer 2-14 is connected to the first register selection circuit 2-1 based on the control of the write signal 2-11.
The write data is supplied to the memory cell section 2-1 via the write data line 2-19 selected by the column selection signal 2-6, and the write data is supplied to the first register column 2-4 selected by the column selection signal 2-6. Write to 8-bit registers 2-3 at the same time.

Next, the operation of the inter-register calculation of CPU1-1 will be explained with reference to the timing diagram of FIG.

During the period T4, two pieces of operation data from the general-purpose register 1-2 are transferred onto the first data bus 1-5 and the second data bus 1-6.
They are respectively output to the top and simultaneously written to the first temporary register l-7 and the second temporary register 1-8, respectively, in synchronization with the timing t5. At the same time, t
ALUI-3 starts the arithmetic and logic operation operation in synchronization with timing t6, writes the operation result to ALU latch 1-9 in synchronization with t6, and outputs the operation result on the first data bus 1-5. Then, it is written to the general-purpose register 1-2 in synchronization with 17 within the period T5. When the register set selection signal (-10) changes due to an interrupt or task switching,
When a different column selection signal (by the column selection circuit 2-2) becomes active, the register set is automatically switched, and at the same time, the old register information is retained in the memory cell, and the execution environment switching software (Effect of the invention) As explained above, the general-purpose register Fi according to the present invention is completely unnecessary.

It is not only possible to execute operations between registers at high speed compared to conventional methods, but also to use the interrupt program level and task number as a register set selection signal to select a predetermined memory cell. It is possible to perform execution environment switching processing at extremely high speed.

According to the present invention, it is possible to easily increase the capacity of a general-purpose register, to easily realize a large improvement in processing capacity, and to have a very high practical effect.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a CPU having a general-purpose register according to the present invention, FIG. flIJ2 is a detailed block diagram of a general-purpose register according to the present invention, and FIG. FIG. 4 is a block diagram of a conventional CPLI, and FIG. 5 is a timing diagram showing the operation timing of a conventional CPU. 1...Based on the present invention<CPU, 4...
Conventional CPUt, 1-2.4-2...General-purpose register, 1-3°4-3...ALU, 1-4.
4-4 Old timing control circuit, l-5...
・First data bus, 1-6...Second data bus, 4-5・Old...Data bus, 1-7.4-6...
...First temporary register, 1-8.4-7.
...Second temporary register, 1-9.4-8
...AL[Jlatte, 1-10...Register set selection signal, 2-1...Storage cell,
2-2... Memory cell, 2-3... First
No. 8 register, 2-4...-first register column, 2-5...column selection circuit, 2-6...
... Column selection signal, 2-7 ... Control gate, 2-
9...First read signal, 2-10...
...Second read signal, 2-11...Write signal, 2-12...First register designation signal, 2-13...First register selection circuit, 2-
14... Input/output buffer 7, 2-15...
・Second register designation signal, 2-16...second
register selection circuit, 2-17...output driver, 2-18...data line, 2-19...
...Write data line. Agent: Susumu Uchihara, patent attorney:,:,:,:
,J. Figure 2 Figure 3 4-3 Figure 4 4-4 4-r collapse S
figure

Claims (1)

[Claims] In an information processing device in which a general-purpose register and an arithmetic unit are integrated on a single semiconductor chip, the general-purpose register has p register sets each consisting of n m-bit registers, and the general-purpose register includes a column selection circuit and a plurality of row selection circuits. and a memory cell, the memory cell has a structure of p columns and n*m rows, the column selection circuit selects one column from p columns, and the plurality of row selection circuits select n*m columns. A general-purpose register characterized in that data in a plurality of m-bit registers is independently selected from bits and outputted to the arithmetic circuit.