JPH02277125A - Register bank circuit - Google Patents

Abstract

PURPOSE:To eliminate the need for the selection of the memories repetitively until the bank numbers are switched when the accesses are given to the registers included in a bank by using a bank number decoding signal and selecting all registers equivalent to one bank. CONSTITUTION:A data bus interface DBI 61 transfers the instructions, the data, etc., between a program memory and a data memory via a data bus DB 69. In this case, the necessary address information is produced by an address generating unit AGEN 62 and supplied via an address bus interface ABI 63 and an address bus AB 68. The instructions read out of the memories are held by an instruction buffer IBUF 64 and then sent successively to an instruction decoder IDEC 65 to be decoded there. A control signal generating unit CONT 66 produces the control signal of each part necessary for the execution of the decoded instructions. A REGISTER BANK block 51 is the assembly of registers turned into banks that is used by a programmer.

Description

DETAILED DESCRIPTION OF THE INVENTION [Objective of the Invention (Industrial Application Field) The present invention is suitable for improving a microprocessor part by 1% with respect to a register bank circuit.

(Prior art) This type of register bank circuit uses RAM as shown in Figure 3.
(read/write memory) 21, a register pointer 22 that holds a register number, a bank pointer 23 that holds a bank number, and upon receiving the outputs of the bank pointer and register pointer.

It has an address generation circuit 24 that generates addresses.

A register bank system was used in which any register could be read or written by giving the address to RAM JJ.

(Problem to be solved by the invention) However, the above method had the following drawbacks.

(a) To use RAM 21 as a register.

It takes a long time (access time) from when an address is given until the data on the data base 25 becomes valid, and when this register bank method is introduced into a microprocessor etc. Every,
The above-mentioned processing time is required, and the execution speed of microprocessors and the like is limited, so it is difficult to introduce this method into systems that require high-speed processing.

fb) Also, since the normal R notification is used as a register, it is not possible to access data in two different registers at the same time. Therefore, when this register bank circuit is introduced into a microprocessor etc. when processing data.

Compared to a method that allows access to two registers simultaneously,
Since the two registers must be accessed one by one, processing speed becomes slower.

Therefore, in order to improve the drawbacks shown in FIG. 3, a register panter system as shown in FIG. 4 will be considered.

This method uses a plurality of register latch groups 31, each forming a register latch group, and register pointers 32-1, . It has a register pointer 32-2, a non-link pointer 33 that holds a bank number, and a decoder 34 that receives and decodes the outputs of the register pointer and bank pointer. Any number 9 from the register latch group 31 of
Up to two registers in the link can be selected. This plural register latch group 31 is.

Each is associated with a bank number. here.

Let us take as an example a register bank having an 8-bank configuration in which each bank has 8 registers. The details are shown in FIGS. 5 and 6. As shown in the figure, each register latch group 3 is composed of eight registers, register latches RO to R7. Further, the output of the decoder 34 is eight sets of bank select signals (BS7 to n5o), and each set is connected to the register latch group 31 in correspondence with the bank number and l to l. or.

Each set has two register pointers 32-1゜32-
Since each register is selected by each of 2, it is further divided into two groups.

(eg B57a and n57b) and each set consists of eight control signals. Further, the eight control signals are connected to the register latches R, 0 to R7 in a one-to-one correspondence with the register number. Therefore, independently from each set, register latch RQ-R7
It is possible to select one of the following. The register latches selected for the 10th group are connected to the data bus 35-1, and the register latches selected for the second group are connected to the data bus 35-1.
Data is read and written through 5-2t-.

A microprocessor incorporating such a register bank circuit is capable of high-speed register transfer and can improve execution speed.

However, this method has a first-order problem compared to the method shown in FIG. 3 above.

(al) Because the registers are constructed using register latches, there is a problem that the scale of one circuit becomes larger compared to the method using RAM shown in Fig. 3.For this reason, for example,
When trying to realize a circuit like the one shown in Figure 5 on an integrated circuit,
This method requires an area more than twice as large as the method using RAM, and in some cases, it may not be possible to secure the required number of registers.

(b) The number of control lines (bank select signals and register select signals) output by the decoder 34 is large, and when used in an integrated circuit, the area required for wiring is larger than in the RAM system.

It may become complicated to handle.

(e) Regarding flexibility when increasing or decreasing the number of banks, it is necessary to redesign the decoder section as the number of banks increases or decreases.
This method requires a large circuit change because the scale of the decoder is large. This becomes a major constraint when realized on an integrated circuit.

Therefore, an object of the present invention is to realize a register bank system that is small-scale even when the number of registers x number of banks is large, can be realized with a simple circuit, and is fast. This realizes a register bank circuit that is flexible and has high cost performance.

[Structure of the Invention] (Lesson jlSLt - Ninth Means and Effects to Solve) The present invention consists of a bank in which each row is composed of a plurality of blocks of registers, and each column is connected to a dedicated memory bus, which is readable and writable. A register array made up of memory.

bank number holding means for holding one or more bank numbers; and 79 link selection means for selecting a series of data groups in the memory based on the output of the bank number holding means;
The register number holding means holds one or more register numbers, and the register selection means selects data in one or more registers for the series of data groups based on the output of the register holding number means. , is a register bank circuit in which the series of data groups is constituted by data of all registers in one bank.

That is, in the present invention, the memory is configured such that all registers of the non-link corresponding to the bank number are selected by only the decode signal of the bank number. Then, select one bank molecule from the memory.

By holding it, it becomes possible to bury the helmet at high speed.

Furthermore, the memory is connected to a multiplexer as register selection means, so that reads and writes are processed through this multiplexer. or.

This multiplexer is controlled by the register number so that any register can be selected, and if necessary, multiple multiplexers can be prepared to access multiple registers at the same time.

Furthermore, the bank number and register number are held for one period by the bank number holding means and the register number holding means. Therefore, for example, when one bank number is continuously designated and data is processed between registers within one bank, the time required to set the first address can be shortened. In other words.

- By simply specifying the bank number, the bank number holding means holds it, and if the bank number continues to be specified, there is no need to specify the bank number again. As a result, a microprocessor using the register according to the present invention can achieve a high speed of loading.

(9) Unlike the structure where the register pointer is wired directly to the bank, the area does not increase, and a relatively large number of registers can be configured in a small area.

(Example) The present invention will be described in detail below with reference to the drawings.

FIG. 1(5) is a schematic diagram of an application of the present invention. This is a block diagram of the main part of the microprocessor, and each functional block is as described below.

DBI 6 J data bus interface 69
゜Instructions and data are exchanged with the program memory and data memory via the data bus DB69f.

The address information required at this time is the address generation unit A.
GEN 6 j and provided by the address bus interface ABI 53 address address AB6#. Instructions read from memory are held in an instruction buffer IBUF 64 and sent to an instruction decoder I
The data is sequentially sent to the DEC65 and decoded.

Control signal generation unit) C0NT 66 generates control signals for each unit necessary for executing the decoded instruction.

The ALU 5F is an arithmetic and logic unit that processes various operations such as arithmetic operations and logical operations. REGI 5T
ERBANK block 51 is a collection of banked registers used by the programmer. Bank pointer BP5 holds the register bank number.
3, the decoder DEC54 decodes the contents of the bank pointer and outputs the register bank selection signal.
It is. The register pointer (R
PJ) 5.5-JR.

(RP2) 55-IR. R8EL5g-R is a selector block for selecting a register designated by this register pointer and outputting its contents. Also, the register pointer (R) holds the write register number in the selected register bank.
P.? )55-IW, (RP4), and 55-JW.

WSEL5g-W is provided as a selector block for selecting the register designated by this register pointer and writing to that register.

These functional blocks are the data bus DBX.

The DB 7 is updated and the data is removed. control signal generation unit) IR which is the output from the C0NT section 66
G3C%IRGy, 0RGx, and 0RG7 are signal lines that transfer register numbers designated by instructions to register pointers, respectively. RPOlx, RPO
2x.

RPO3! And RP04 is an output signal line connected from the register pointer 55 to each selector section 56-R and 5B-W. BPOx is an output signal line of the bank pointer 53, and BSK is a bank selection signal of the register bank 51. CBx and its inverted signal CBX are bit pass signals for each register. BBX is a data signal line for reading bits of each register.

In this schematic diagram, an example will be described in which an instruction to add the contents of the register number and the contents of the register number and store the sum in the register R2 (described later in FIG. 1 (see 11)) is executed.

At this time, it is assumed that the bank pointer 53 has been set to a certain register bank number in advance. The instruction is fetched from instruction buffer IBUF 64.

The command decoder IDEC unit 65 decodes the command and generates each control signal. At this time, the register zero data corresponding to Ro is transferred to the signal line IRGx, and the register zero data corresponding to Ro is also transferred to the signal line IRQyKR.
Register number data corresponding to J is output and set in register pointers RP 1 and RP 2, respectively. Then, the register number data corresponding to R2 is outputted to the signal line 0RGXIIC and set in the register pointer RPJ. Thereafter, by issuing a read signal to the register, the contents of Ro are output from the selector R8EL block 56-R to the data bus DBX, and the contents of R1 are output to the data bus DBF.

Here, one embodiment includes a plurality of data buses DBx.

By using DBF t-, two pieces of data can be moved simultaneously during such processing.

9 data outputted to DBX and Dny are calculated by 22)
Each input is input to both inputs of ALU 6F.

Control signal generation unit) A control signal for addition is output from the C0NT section 66, and addition is performed in the ALU 6fF.

The sum of this addition is output to the data bus DBx and becomes an input to the selector lock VIBEL section 56-W. and.

The write signal to the register is output.
Writing is performed. In this manner, each instruction is executed.

Also, register pointer (RPJ) 55-JR, (RP
! ')55-2R, (RP3)55-IW and (RP
4) 55-; Setting the register number for IW is A
It is possible to set each register pointer at any time when there is free operation, such as during an operation in the LU 67, and the execution of the operation and the setting of the register pointer can be performed in parallel. Therefore, it is also possible to improve geographical efficiency by overlapping the command being executed and the next process t.

More! Figure 1(B) is a schematic diagram of an embodiment of the register bank circuit according to the present invention, and Figure 2 is a diagram showing a further embodiment of the same configuration. That is, in this configuration, each row constitutes a bank consisting of a plurality of blocks of registers, and each column constitutes a readable/writable memory 51 connected to a dedicated memory bus 52, and a bank number holding one or more bank numbers. bank selection means 54 for selecting a series of data groups in the memory, and register number holding means for holding one or more register numbers; 55 and.

A register selection means 56 is provided for selecting data in one or more registers from the series of data groups based on the output of the register number holding means. At the time of reading, the series of data groups is made up of the data of all the registers in one bank, and is output to the memory bus 62.

This output is selected by register selection means 56 and output to data bus 57.

In FIG. 2, the bank number holding means 53 is a bank pointer, the bank selection means 54 is a row (ROW) decoder, and the register number holding means 55 is a register pointer 65-
1 and 55-2, the register selection means 56 is realized by a multi-brancher, respectively.

Even if 1 block B of the register is a 1-bit register.

It does not matter if there are multiple pit registers. Also this example line.

Number of banks: 8. Number of registers in each bank8. It has a 7472 register circuit with each register length being 8 pits and the number of registers that can be accessed at the same time being 2. In this example, the lead,
A writable memory 51, a bank pointer (3 bits) that holds the bank number, and an RO that decodes its output.
The memory 51 is divided into eight banks corresponding to the outputs of the ROW decoder 54. The memory 51 forms one bank with l series of register groups (RO to R7) arranged in the horizontal direction. Set any bank number (0 to 7) to the bank pointer 53.
), its output is input to the row decoder 54, which decodes it and causes one output signal corresponding to the set bank number to transition to a valid state. This selects one of the eight banks of memory, and all registers in that selected bank (
ROS-RF) are each connected to a multiplexer 56 through a dedicated memory bus 52. At this time, each register of the bank that is not selected is electrically isolated from the memory bus 52.

Also, in this example, the multiplexer 56 in Figure 1 is a register pointer 55-1 (3 pits) that holds a register number.
, a register pointer 5B-2 (3B-y)) that independently holds the register number, and a register pointer 55-2 that selects the memory bus 52 according to the outputs of the two register pointers. The memory bus selected by 1 is.

Data bus 57-1 and register pointer 55-, ?
The memory bus 52 selected by K is the data bus 57.
-2 through a multiplexer. As shown in the figure, the meso-repaths (MB, o to MB, .
X! By being connected to the IT-ISf"fi'4 bus 5l-2), reading and writing of each register is performed.

At the time of serial read, one row of bank is selected by the bank pointer 53, and the data from registers RO to B7 of that bank is outputted to the memory bus 52tlC. Among its outputs, register pointer 5s-i.

The nine specified by 55-2 are multiplexer j6
The signals are outputted to data buses 5F-1, 51-;2 via .

On the other hand, at the time of writing, the register pointer 55-J.

55-2 selects an arbitrary number of registers (two in this example), specifies an arbitrary bank (naturally one in this example) with the bank pointer 53, and selects the two registers RKf- of the specified bank. All you have to do is write a mail.

As described above, in the circuit of this embodiment, when the register register is set every time, the eight registers for one bank in the memory 51 are always selected by the ROW decoder 54, and the registers are connected via the memory bus. and connected with a multiplexer. Therefore, reading and writing registers in the bank only requires setting the desired register number in the register pointer. Shi, at the same time, 2
It is also possible to access two different registers.

In this example, the number of banks is 8. Number of registers in bank: 8, each L
/Sistor 8 pits, the number of registers that can be accessed simultaneously is 2, but there is no need to limit it to this, and the bank pointer length and the number of register pointers.

Any register bank circuit can be constructed by changing the multi-branch register, etc.

Furthermore, an example of the structure of the register bank of the present invention will be explained by taking as an example the case where the register bank 51 in FIG. 1(5) is configured by a register model as shown in FIG. 7.

FIGS. 7(A) and 7(B) show the register model.

Each register R has a minimum unit configuration of 101 for storing l data, from pit o (bo) to bit n (bn) t.
It consists of n+l bits.

The number of registers R from RO to Rk constitutes one register bank. Further, this is a register model in which the register bank is composed of m+1 banks from BANK O to BANK m. For example, in a 4-pit register model, signals are handled every 4 pits in each register, and the subsequent selectors, data buses, etc. also correspond to 4 pits and a nine-circuit configuration is applied, but the single register in this application can handle arbitrary signals. It can be applied to the number of bits.

The number of bits is called the number of bits per data processing unit.

One BANK in FIG. 7 is composed of registers 101 having the minimum number of bits per data processing unit. Tsutb.

If the register is for 8 pits, one register is made up of eight minimum registers 01. A plurality of registers B are configured and
) is formed.

As shown in the examples of FIGS. 8 and 9, each register in the register/4 link is arranged such that registers having the same register number are arranged in the same column.

Also, as in the example in Figure 1O, each bit z in the register
oxFi, bits of the same register number are arranged so as to overlap in the column direction. Note that in each pit column, one pair of precharge circuit PR and one pair of sense circuit SA are arranged in one column.

FIG. 11 shows a detailed circuit example of these cells CILL, PRM, and eight cells. CB and its inverted signal CB are bit paths of the cell string. BS is a cell row selection signal 1L. When this signal is at a high level, a cell is selected. PRC is a control signal for the tree charge circuit,
When this signal is at low level, bit paths CB and CB are precharged and set to high level. 8NS and SN
S is a control signal for the sense circuit, and when 8NB is at a low level and BNB is at a low level, the state of the bit path is secured in the r-ta held by the selected cell.

BB is a read data signal line for each bit.

The state of this signal corresponds to one bit of read data. Further, vdd in FIG. 1 is a power supply.

A CELL for directly storing data as charges is a pit line pair CB, CB, and a first FET whose one end is connected to the bit line CB and whose dart is connected to the row selection signal line US.
JJJ, one end of which is connected to the other end of this first FETIJJ, a ninth inverter 113, and this first FETJJ
A second inverter 114 whose one end is connected to the other end of J, and the other end of this first inverter 11B and the second inverter 1
One end is connected to the other end of 14, and one bit I! ACB is connected to the second FET JJJ, and dart is connected to the row selection signal line B.

In addition, the circuit that supplies a positive potential, the NoriCharge circuit PR, is
Positive potential power supply Vdd and pit line pair CB.

CB and one end thereof is connected to this bit line CB.

The other end is connected to the positive potential power supply Vdd, and the round part 1 FET
115, and the other end is connected to the other pin aCB, and the other end is connected to the positive potential power supply Vdd, and the round part 2F
It consists of ET J J 6. Also, the first FET
715 and the dart of the second FET IJ6 are connected to the precharge signal PRC.

The sense amplifier that determines the potential of the bit lines CB and CB connects the positive potential power supply Vdd and the pit line pair CB and CB.
and the first FIT J whose one end is connected to the bit line CM
17 and % The other end of the first FET 117 is connected to its one end, the other end is connected to the other bit line CB, and the second FET whose r-) is connected to the bit line CB.
J J j and one end are connected to the bit line CB, and the first
FET J J 7 r-) and other pin) #C
BE sono f-) is connected to 9#l3FET 119,
One end is connected to the other end of the third FET 119, the other end is connected to the other bit line CB, and the second FET
71 The dart is connected to the dart of B and the round part 4FE
T120, one end is connected to the positive potential power supply Vdd, and the first
The other end is connected to the other end of FETJJ7, and the control signal S
5th FET J j J to which NS is supplied to Dart;
The sixth FET 1jj is connected to one end of the fourth FET 120, the other end is connected to the ground potential, and the control signal 8NS is connected to r-t.

FIG. 12 shows register pointer RP1 in FIG.

This is a detailed circuit example of RPj, RPJ, and RPJ. In the example of FIG. 1 (5), data buses DBx and DBF and the next signal lines IRQX, IRGy, 0RGx,
Since it is powered by three people with one of the 0RGy, a three-person multiplexer is added to the input of one normal latch circuit. This circuit block L3g in FIG. 12 is arranged in the required number of bits.

14) If the number of registers in one bank is 8, it is 3 bits, and if there are 16 registers, it is 4 bits.

SEL 3 in FIG. 12 is a selection signal that specifies which of the three inputs to select.

When this signal becomes high level, it becomes input to the input register pointer corresponding to ζ. LR is a register number setting signal of a register pointer.

When LR becomes low level, input data is taken in.

When the level becomes high, the data will be retained. The input signal in Fig. 12 is DBx O to DBx
n means DBx data bus in FIG. 1 (5),
DB) FO to DByn means the DB7 data path in the first figure), and from l10RGiO to l10R
GiJ is the signal line IRGx, IRG in the first round
y, ORJ:ix.

It means oRay. RPOO to RPOj are the outputs from the register pointer, and the signal lines RPOIX, RPO2x, RPO3x in the first figure)
, meaning RPO4x.

FIG. 19 shows an example of the timing of updating the register pointer. The upper register number “01” (1
(hex) t-RPJ and register selection signal (R
80 to R8k).

Figure 13 shows the write selector WBEL in the first
56-W is a detailed circuit example. Register pointer RP3
, RPJ output RPO30 to RPO3J and RP
RPO4J is input from O4Q, decoded by decoders RP3DEC and RP4DKC, and selection signals R830x, R831! corresponding to the registers to be written are generated. ,
R840F.

RI941F, ...... is generated. 1st
In the example in Figure (4), there are write data paths from two data buses, DBX and DBF, so the corresponding write signals WRx and WRy are combined with the register selection signal to become the actual write signal. .

This write signal is commonly connected for each register, and one write signal writes to all pits of one register. Also.

SO, which is a component of the write selector WBEL section, is connected to data buses DBx and DBF, and whether one of them is selected is determined by the write signal.

ζNow, the data on the data bus DBx is transferred to the register ROK.
Taking I input as an example, the operation is as follows. A register number corresponding to RO is set in register pointer RP3. The output of this RP3 is encoded by the RP3DEC, so that the signal to R830 becomes high level, and the other selection signal R831! .

...is a low level. Here, when the write signal WRx on the data bus DBx side becomes high level, N
Only the output of ANDQ becomes low level. This NAND
The buffer on the DBx side of the SO block corresponding to R(> connected to the output of O becomes active, and the data on the DBF is transferred to the bit path CB corresponding to each bit.
OO, CBOl, ......, supplied to CBQn,
The inverted signals of each data are bit paths CBOO, C
BOI,=., is supplied to CBOn. At this time.

Bit paths corresponding to other register numbers will not be affected in any way. In the cell part, a selection signal (BS
) is at a high level, and the grid charge circuit PR and sense circuit 8A are inactive. In this state, DB is placed on the bit path corresponding to each pit of RO.
Since the x data is forcibly supplied, the data on the bit path will be written to the cell of the bit corresponding to RO among the selected cells. In other cells, the state of the bit path does not change, so nothing changes. After the time required for writing has elapsed,
The seedling signal is low level.

The bit path corresponding to 41ROK, which corresponds to W8KLoRO, which has been supplying the data on DBx to the bit path, is inactive, but the bit path corresponding to 41ROK retains the written data, and it is in the same state as if it had been read. Become.

In this way, writing to the register is performed. Therefore, there is no need to set up a decoder corresponding to the write address or precharge the bit path, which is required when using an existing RAM, and there is no need to perform any operations in response to a reread request after a write operation. You won't need it.

Figure 21 shows data “55” (hexadecimal) on ROK DBx and data “AA” (hexadecimal) on DBF in R1.
An example of the timing when writing simultaneously is shown below.

Lead selection R8KL in figure 14 company figure 1 prisoner
This is a detailed circuit example of 5g-R. register pointer R
RPOlj and RP from RPOIO of PO, RPI output
Decoders RPIDEC and RP2DE with O2j as input
By C.

Register selection signal R810X, R811x, R
820x.

R821y, . . . are generated. 1st
In the rotation example, there are two read data paths, data buses DBx and DBF, and the corresponding read signals RDx to the DBx side are RDx <! : It is combined with the read signal RI)F to the DBy side and becomes the actual read signal of the 1 selection register. This readout signal is commonly connected in register units, and one readout signal reads out all the pits of one register. In addition, S! which is a component of the lead selection R8EL part! are the read data signal lines BBOO and B of each register.
BOI, . . . are used as inputs to selectively output to the DBz data bus and DB7 data bus. Even though it is a read operation, the data in all the pits of a certain register is read out.

It is already being supplied as an input to 8I. Therefore, set the register number corresponding to the register you want to read in the register pointer.

By applying the read signal, data is immediately outputted from the selector circuit SI to the desired data buses DBx and DBy.

As described above, the register of the present invention requires access time only at the time of register bank switching, and the access time is long enough to cause no problem in this operation.

Figure 20 shows the contents of registers RO and R1, t-DBx and DB.
An example of the timing when simultaneously reading 3F is shown.

By adopting this circuit configuration, high-speed operation is required,
Furthermore, it is possible to realize a register that requires rereading after writing with a simple configuration.

FIG. 15 shows decoders RPIDEC and RP2DEC that generate register selection signals from register pointer outputs.

This is a detailed circuit example of RP3DEC and RP4DEC.

If the register pointer is 3 bits, the NA is 8.
It is composed of ND-N07 circuits, and if it is 4 bits, it is composed of 16 NAND-N07 circuits.

FIG. 16 is a detailed circuit example of the bank pointer BP.

In the example shown in figure 1), the bank pointer is the data pointer.
1 because it has two inputs: DBx and DB3F.
A two-man power multi-breather is added at the input of a normal latch circuit. The selection signal of this multi-breather is 8
It is EL2. The latch signal of the bank pointer is LB, and when LB is at low level, the data on KDBx or DBF is inputted via the multi-breather, and when it becomes high level, the data is held. npoo
, BPO1 is the output signal of the bank pointer, and the first
This means BPOx in Figure (5)). When the number of register banks is 8, the register pointer is composed of 3 bits, and when there are 16 banks, it is composed of 4 bits.

FIG. 17 is a detailed circuit example of the decoder DEC in FIG. 1 (5). BPO which is the output signal of bank pointer BP
O to BPOI f: A decoder circuit that receives input and generates a bank selection signal (Boo to BSm). The bank selection signal is connected to the row selection signal B8 of the register bank 51, so that a cell in one row of the register bank 51 is selected by the bank pointer.

The DI8 signal S is a bank selection threading signal for keeping any selection signal inactive during the period when the bank pointer is switched, since the bank selection signal becomes unstable.

FIG. 18 shows an example of register bank switching timing. In this example, register bank I'?: is selected by inputting data '01'' (hexadecimal number) on the DBx data bus until all data bits of all registers of that register bank 1 are read. It shows the timing.

When the data latch signal (LB) to the bank pointer becomes active, the DIS signal becomes active to inhibit the bank selection signal during that period. Further, a PRC signal NOFUS is generated using this period to precharge the pit path in the register bank 51. This is necessary so that data in cells on the newly selected register bank 51 will not be destroyed. When the latch signal (LB) becomes inactive, the bank selection prohibition signal (0119) also becomes inactive, and only the register bank 1 selection signal (1191) becomes high level.

This selection signal selects the cell row corresponding to the register bank 51, starts driving the bit path connected to each cell with the data of the cell, and then the sense circuit (SA)
't-Apply SN3.8NS signal pulse to work. When the sense circuit (SA) operates, register bank 5
The data on the bit paths within the bit path are determined to their respective states.

In this way, register bank switching and the data of all bits of all registers in the switched register bank are read.

The read data signal MACB B'') is supplied to the input of the read selector R8EL circuit via t-.

The charge circuit (PR) and the sensor circuit (SA) in the register bank 51 operate at the time of register bank switching.
Register read operation and 81! It is a trap so that it does not work in the input operation.

As is clear from the above detailed description of the present invention, the present invention allows data to be accessed without requiring the address operation required when using an off-the-shelf RAM. This makes it possible to easily and inexpensively create a register bank circuit with a small circuit scale despite its large capacity.

[Effects of the Invention] In the conventional system shown in FIG.
Since one address is generated from the bank number and register number to access the register, the address has to be given again every time the register is accessed, even if it is in the same bank. In principle, only one register could be accessed at a time.

In contrast, the present invention uses a bank number decode signal to
All registers for one bank can be selected, so when accessing registers in a bank, all you have to do is switch the register selection means such as a multiplexer depending on the register number, so you can select the memory until the bank number is switched. There is no need to redo it. Also, multiplex? By providing multiple register numbers, it is possible to specify multiple register numbers, and this allows access to multiple registers at the same time. This eliminates the need for access time for each access to the register, and allows for high-speed access since there is an access time only when banks are switched.

Next, in the conventional systems shown in Figures 4 to 6, the registers are formed using register latches, which increases the size of each circuit and increases the number of outputs of the decoder. It had a very large drawback. Furthermore, the design of the decoder, which is a large circuit, must be changed in response to an increase or decrease in the number of registers or banks, resulting in poor flexibility.

In contrast, the present invention is suitable for use as a register in a microgrocer, and requires only small decoders, multiplexers, etc. Also, the number of registers can be increased or decreased.

It is highly flexible because it only requires one small-scale decoder circuit and an increase or decrease in memory.

As described above, according to the present invention, a register bank circuit having a single circuit scale, high speed, and high flexibility in the number of registers can be easily realized at low cost. In particular, when it is incorporated into a microprocessor or integrated circuit, it can fully demonstrate its capabilities in terms of chip area occupation rate, system capacity, etc., and can realize an excellent product with good cost performance.

[Brief explanation of drawings]

FIG. 1 is a configuration diagram of an embodiment of the present invention, FIG. 2 is a partially detailed diagram of the configuration, #! 3 to 6 are register bank circuit diagrams to which the present invention is not applied, FIG. 7 is a conceptual diagram showing the structure of a register, and FIG. 8 is a conceptual diagram showing an example of register bank arrangement.
Fig. 9 is a conceptual diagram showing a register arrangement sequence, Fig. 1θ is a conceptual diagram showing a bit arrangement sequence, Figs. 811 to 17 are detailed circuit diagrams of each part of the above embodiment, and Figs. 5 is a timing chart showing the operation of each part. 51...Register array (register bank block)
, 52... Memory bus, 53... Bank number holding means, 54... Decoder, 55... Register number holding means, 55-IW to 554B... Bank 4 inter, 5
6... Register selection means, 56-W... Write side selector, 56-R... Read side selector, 5
'i-1, 57-2...Data bus, 61...Data bus interface, 62...Address generator,
63...Address bus interface, 64...
Instruction buffer, 65... Instruction decoder, 66... Control signal generation unit. 67... Arithmetic logic unit, 68... Address bus, 69... Data bus. Figure Figure Figure Figure 9 Figure Figure 18 Figure 191g

Claims (2)

[Claims] (1) A register array in which each row constitutes a bank consisting of multiple blocks of registers, and each column constitutes a readable/writable memory connected to a dedicated memory bus, and all blocks in one bank in the memory. A register bank circuit comprising bank selection means for selecting a register. (2) bank number holding means for holding one or more bank numbers; said bank selection means for selecting a series of data groups in said memory based on the output of said bank number holding means; and one or more registers. Claim 1 characterized by comprising: register number holding means for holding a number; and register selection means for selecting data in one or more registers for the series of data groups based on the output of the register number holding means. The register bank circuit described in .