JPS6017538A - Instruction processing device - Google Patents

Abstract

PURPOSE:To process simultaneously calculation of the operand address, etc. for 2 operands or above, by cutting out the object instruction in accordance with the instruction length and constituting the instruction at a time so that the instruction can be preserved at the instruction register. CONSTITUTION:The object instruction can be cut out in accordance with the instruction length and at a time this instruction can be preserved at the instruction register. For example, the object instruction is cut out by an instruction cut- out circuit 102 from an instruction buffer 101 in accordance with the instruction length and the instruction is preserved at an instruction register 103. Next, the base register value designated by the B1 portion and B2 portion of the instruction register 103 is read out through signal lines 200 to 203 from a general register 104, is inputted to an adder 105 and an adder 108 respectively and the output of the D1 portion and D2 portion is inputted through signal lines 204 to 205 to the adder 105 and adder 108 respectively. And, the address is calculated by the input data with the adder 105, etc., and is inputted through a memory device 106, etc., to an operator 107.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to instruction processing, and more particularly to an instruction processing device suitable for processing at high speed an instruction that reads and performs an operation on two or more operands from a storage device. .

[Background of the invention]

An example of the format of an instruction requiring operands on two storage devices is shown in FIG. 1, bits 0-7 represent the operand length (OP), bits 8-15 represent the length of the operand, bits 16-19 and bits 20-31 represent the base part (Bl), respectively. ), dust at the displacement part (Dl),
The operand address representing the general-purpose register number and deviation value used to calculate the address of the operand (first operand) on the storage device is obtained by adding the value of Dl to the contents of the register numbered B1.

Bits 32-35 and bits 36-47 represent a general-purpose register number and offset value used to calculate the address of the second operand (second operand) of the storage device.

2, bits 8-11: i, . . .
2-15 is the first loss, the second loss i 2A<Land and I)
2 Represents the length of the operands 1 to pl-others are the same as 1.

3, bits 0-15 represent the operation code, and bits 16-47 are the same as 1.

Conventionally, an instruction processing device for instructions having a formatter as shown in FIG. 2 was constructed as shown in FIG.

Here, reference numeral 11 denotes an instruction buffer that temporarily holds a plurality of instructions read from the storage device, and necessary instructions from among them are transferred to an instruction register 13 by an instruction extraction circuit 12.
Take it out. Conventionally, the instruction extraction circuit 12 has a 4-byte instruction extraction function, and the instruction register 13 has been prepared for 4 bytes.

When calculating the operand address of each instruction shown in FIG.
Input to adder 15. At the same time, D1 of the instruction register 13
The address of the first operand is calculated by inputting the part directly to the adder 15. As a result, the memory device 16 is referred to using the sound, and the first operand is read out to the arithmetic unit 17. Next, the instruction extraction circuit 12 takes out the remaining two instructions (2 bits) to the fc instruction register 13. As in the case of the first operand, the contents of the general-purpose register designated by the B2 part are read to the adder 15 via the signal line 20.21, and the B2 part is directly input to the adder 15 via the signal line 22, and Performs address calculation of operand. The storage device 16 uses the result.
, and reads out the second operand to the arithmetic unit 17. Thereafter, the arithmetic unit 17 can start executing the operation indicated by the operation code.

In this way, the address calculation of the operand of each instruction shown in FIG. 1 and the operand reading from the storage device are performed in the first
Although the operand and second operand can be processed independently, the instruction extraction circuit 12 and instruction register 13 are only 4 bytes long, and the general-purpose register 1
4 has one readout port, one adder 15 for address calculation, one storage device 16, and so on. A problem arose in that the start of calculation execution had to wait until the end of two storage device references.

[Purpose of the invention]

An object of the present invention is to calculate an operand address and use it to refer to a storage device for two or more operands at the same time, in order to process the instruction having the same function as shown in FIG. 1 at high speed. An object of the present invention is to provide an instruction processing device capable of processing instructions.

[Summary of the invention]

In order to calculate the operand address and use it to refer to the storage device independently and simultaneously for two or more memory operands, first transfer the number of bytes corresponding to the instruction length from the instruction buffer to the instruction register at one time. An adder for calculating the operand address and a storage device that can read out the operand tube using the addition result are prepared separately for each operand, and each is configured to be able to operate independently and simultaneously. Just do it.

[Embodiments of the invention]

Hereinafter, one embodiment of the present invention will be explained with reference to FIG. 10
1 is stored in the instruction buffer. Reference numeral 102 designates a circuit that extracts the necessary number of bytes from the instruction buffer according to the instruction length, and is an instruction extraction circuit that can extract a maximum of 6 byte instructions. Instruction register 103 can hold 6-byte instructions. The value of the pace register specified in the instruction register 1030B1 section is read from the general-purpose register 104 using signal lines 200 and 201 and input to the adder +1 105. On the other hand, the value of the pace register designated by the B2 section of the instruction register 103 is read from the general-purpose register 104 using the signal lines 202 and 203'5, and is input to the adder 2108. Reading of the registers designated by portions B1 and 52 can be performed independently and simultaneously. The D1 and B2 parts of the instruction register are each seven adders≠1105
, directly input to adder +2108. Adder 1105
, the adder≠2108 performs all address calculations using the above input data (r), and uses the result to calculate the storage device cost 1 10
6. Memory f: Setting 2]09♀ is referred to and the read operands are transferred to the arithmetic unit 107. Arithmetic unit 107
The execution of the operation in can be started at the same time as the reading of the two operands is completed.

As described above, according to this embodiment, each 6-byte instruction shown in FIG. 1 can be extracted to the instruction register 103 by t1 times. Furthermore, two read ports are provided for the general-purpose register 104, and an adder that can calculate an operand address using the value read from each read port using the value in the instruction register 103, and a storage device that can be referenced by the calculated address are provided. By providing two sets of each, a series of processes necessary for reading the first operand and the second operand can be performed simultaneously and independently. As a result, the calculation in the storage device reference diameter calculator 107, which could conventionally be started twice, can now be performed immediately after one storage device reference is completed. Memory reference is conventionally a time-consuming process, but in this embodiment, the processing time can be halved.
Very effective.

〔Effect of the invention〕

According to the present invention, the circuit that extracts the instructions according to the number of bytes of the target instruction can take out the instructions at once to the instruction register, and after the instructions are fixed in the instruction register, a completely different general-purpose register reading is performed. By using paths, adders and storage devices that can operate independently of each other, two or more operands can be read completely independently and simultaneously, so that the portion of the instruction required to calculate the address of each operand can be Compared to the conventional configuration, which repeatedly sets registers in sequence and repeatedly uses one general-purpose register read path, adder, and storage device to read multiple operands sequentially, each operand can be read faster. As a result, the start of arithmetic processing in the arithmetic unit can be accelerated.

[Brief explanation of drawings]

FIG. 1 shows an example of the instruction format targeted by the present invention. FIG. 2 is a schematic configuration diagram of a conventional instruction processing device. FIG. 3 is a schematic configuration diagram of an instruction processing device using the present invention. 13.103...Instruction register, 14,104...
General-purpose register (GR), 15, 108, 105... Adder for calculating operand address, 16, 106° 109
...Storage device, 17,107...Arithmetic unit, 11゜1
01...Instruction buffer, 12,1.02...Instruction extraction 203 Bacteria 1 Figure) 52 Figure 3

Claims (1)

[Claims] 1. A device that processes instructions with two or more memory operands has a function of extracting the target instruction according to its instruction length and holding the instruction in an instruction register at a time, and a group of registers each having a function of independently reading out the values necessary to output the operand address tX using instruction data;
An instruction processing device comprising an address adder capable of independently and simultaneously adding the value read from the register group and the value determined by the instruction data for each operand and outputting the addition result. 2. The instruction processing device according to item 1, which is characterized in that it includes a storage device capable of independently and simultaneously reading the corresponding operands by using the result of address addition for each operand.