GB1593136A - Data processing - Google Patents

Description

(54) DATA PROCESSING DEVICE (71) We, VALERY FEDOROVICH GUSEV, of ulitsa Karbysheva 13-a, kv. 35, Kazan, USSR., GENNADY NIKOLAEVICH IVANOV, of ulitsa Dekabristov, 184-a, kv. 22, Kazan, USSR., VLADIMIR YAKOVLEVICH KONTAREV, of ploschad Junosti, 4, kv. 3, Moscow, USSR., GENRIKH ISAEVICH KRENGEL, of ulitsa Obragimova, 45, kv. 49, Kazan, USSR., EVGENY OLEGOVICH POLIVODA, of ulitsa Kuibysheva, 32, kv. 24, Kazan, USSR., ALEXANDR NIKOLAEVICH SKVORTSOV, of ulitsa, Volodarskogo, 8, kv. 22, Kazan, USSR., JURY IVANOVICH SCHETININ, of 103536, korpus 503, kv. 106, Moscow, USSR., VYACHESLAV YAKOVLEVICH KREMLEV, of Berezovaya alleya, korpus 423, kv. 81, Moscow, USSR., MANSUR ZAKIROVICH SHAGIVALEEV, of ulitsa Karbysheva, 17, kv. 75, Kazan, USSR., and AZAT USMANOVICH YARMUKHAMETOV, of ulitsa Adelya Kutuya, 12, kv. 23, Kazan, USSR., all USSR citizens, do hereby declare the invention, for which we pray that a patent may be granted to us, and the method by which it is to be performed, to be particularly described in and by the following statement:- This invention relates to data processing devices intended for processing data represented by variable length formats.

The invention is applicable to the construction of computer processors.

According to the present invention, there is provided a data processing apparatus for processing variable multibyte data fields, comprising a control unit arranged to control the actions of elements of the apparatus, a store arranged to store initial operands, intermediate results and the processing result at independent addresses, said store having a first input and a first output connected to a first data exchange bus, a second input and a second output connected to a second data exchange bus and a third input connected to the output of an arithmetic-logic unit, each of said buses having an additional input and output; a data shift unit having a first data input and output and a first control input connected to the first data exchange bus, and a second data input and output and a second control input connected to the second data exchange bus, said data shift unit being arranged to effect shifting of the data supplied thereto from the data exchange buses in accordance with control data received through the control inputs; first and second data switches, connected respectively to the first and second data exchange buses, for supplying first and second inputs respectively of the arithmetic-logic unit with data from the respective data exchange buses and for masking the data according to signals from said control unit and a mask having a byte structure which is applied to each of said switches from a data masking unit; said data masking unit having a first control input for selecting the mask class in accordance with data supplied thereto from the first data exchange bus and a second control input for selecting the mask type within the selected class in accordance with data from the second data exchange bus so as to form and transmit to said first and second switches a mask serving to null unwanted bytes within data; said arithmetic-logic unit having its output connected to the store and performing arithmetic and logic operations on data applied thereto from said first and second switches; said data shift unit comprising a shift parameter forming means for producing signals denoting the value and direction of a required shift, said shift parameter forming means having a first data input for receiving data indicating the position within a word of a byte relative to which alignment is to be performed, said first data input being connected to the second data exchange bus by way of one of said control inputs of the data shift unit, said shift parameter forming means having a second data input for receiving data indicating the position of a byte which during the data shifting process must be shifted to the position indicated by the data received at said first data input, said second data input being connected to the first data exchange bus by way of the other of said control inputs of the data shift unit, data shift control means having its input connected to said shift parameter forming means and serving to produce control signals, denotive of the value and direction of a required shift, that are applied to a data shift register of a capacity of at least two words, said data shift register having a first data input, which is connected by way of said first data input of the data shift unit to the first data exchange bus, having a second data input which is connected by way of the second data input of said data shift unit to the second data exchange bus, and having a control input connected to the output of said data shift control means, said data shift register serving to shift the data supplied to it.

Preferably the data shift parameter forming means comprises a data shift code register for storing the position within a word of a first byte relative to which alignment is to be effected, and the position of a second byte which must be shifted during the data shifting process, to the position of said first byte; a decoder connected to the output of said data shift code register and having a plurality of groups of outputs; a first coincidence circuit having inputs connected to a first of said groups of decoder outputs and providing an output denotive of the required direction of a data shift; a plurality of further coincidence circuits each of which has inputs connected to a respective group of said decoder outputs and yields a respective output denotive of a required value of said data shift.

The shift data control means may comprise a data shift direction trigger having its input connected to the output of said first coincidence circuit and a plurality of shift value triggers, equal in number to the number of possible values of data shifts each said shift value trigger having one input connected to an AND gate and another input connected to the output of a respective said further coincidence circuit; a priority circuit connected to the outputs of the data shift value triggers and a decoder having data inputs connected to the outputs of the priority circuit and of the data shift direction trigger, having a control input connected to an output of the control unit and having each of its outputs connected to a further input and a respective said AND gate.

Preferably the data masking unit comprises a mask code register having a first data input for selecting the mask class and connected to the first data exchange bus by way of said first control input of the data masking unit, having a second data input for selecting the type of mask within the selected class and connected to the second data exchange bus by way of said second control input of the data masking unit; a decoder connected to the output of the mask code register and a plurality of AND gates connected to respective sets of outputs of the decoder and serving to form byte masks in accordance with the selected class and type of mask and to apply said masks to said first and second switches.

The present invention may allow operands to be fetched and handled and the result to be written using full words, with the result that the number of accesses to main storage is decreased.

Moreover, the present invention may also allow the current word of an operand to be prepared for handling when the next word of the operand is being fetched, a feature that also tends to increase the speed of operation of the device.

Other features of the invention will appear from the following description of a preferred embodiment thereof, in conjunction with the accompanying drawings in which: Figure 1 is a block diagram of a data processing device for variable length data formats, according to the invention; Figure 2 is a block diagram of a shift parameter forming means; Figure 3 is a block diagram of a shift control means; Figure 4 is a block diagram of a data masking unit; Figure 5 shows the mutual location of two operands; Figures 6a, 6b, 6c, 6d, 6e, 6f show the alignment of the second operand relative to the left boundary of the first operand, in the use of a data processing device according to the invention.

The data processing device for multibyte data fields which is shown in Figure 1, comprises a storage unit 1 having a first data input 2 and a first data output 3 coupled to a first data exchange bus 4 and having a second data input 5 and a second data output 6 coupled to a second data exchange bus 7. An input 8 of a switch 9 is coupled to the data exchange bus 4, while an input 10 of a switch 11 is coupled to the data exchange bus 7. A data masking unit 16 and a control unit 17 are coupled, respectively, to a multichannel input 12 and to a control input 13 of the switch 9, and to a multi-channel input 14 and to a control input 15 of the switch 11. Data inputs 18, 19 of an arithmetic/logic unit 20 are coupled, respectively, to outputs of the switches 9 and 11, and a control input 21 is coupled to the control unit 17, and the output of the arithmetic/logic unit 20 is coupled to an input 22 of the storage unit 1.

Data inputs 23, 24 of the data masking unit 16 are coupled, respectively to the data exchange buses 4, 7, while a control input 25 is coupled to the control unit 17.

A serially connected network is provided in a data shift unit 26 which includes a shift parameter forming means 27, a shift control means 28 and a shift register 29.

A control input 30 and data inputs 31, 32 of the shift parameter forming means 27 are coupled, respectively, to the control unit 17 and to the data exchange buses 4, 7. A multichannel control input 33 of the shift control means 28 is coupled to the control unit 17. Data inputs 34, 35 and data outputs 36, 37 of the shift register 29 are coupled, respectively, to the data exchange buses 4, 7. A control input 38 of the storage unit 1 is coupled to the control unit 17.

There are provided device inputs 39, 40 and device outputs 41,42 coupled to the data exchange buses 4, 7, respectively.

The shift parameter forming means 27, shown in more detail in Figure 2, comprises a shift code register 43 coupled to a decoder 44. Inputs 45, 46 and a control input 47 of the shift code register 43 are used as inputs 31, 32 and 30, respectively of the shift parameter forming means 27. Inputs 48 of a shift direction generating AND gate 49 and inputs 50, 51 of shift value generating AND gates 52, 53 are coupled to respective outputs of the decoder 44. Outputs 54, 55, 56 of respective AND gates 49, 52, 53 are used as a multichannel output of the shift parameter forming means 27 (Figure 1).

The shift control means 28 shown in Figure 3 comprises shift value bistable triggers 57, of which the number corresponds to the number of shift values available. The inputs 58 of triggers 57 are coupled to the outputs, such as 55, 56, of respective AND gates 52, 53 in the shift parameter forming means 27. The outputs of further AND gates 60 are coupled to inputs 59 of the shift value triggers 57.

Inputs 61 of the AND gates 60 are coupled to the control unit 17. Inputs 63 of a priority circuit 62 are coupled to the outputs of the shift value triggers 57. The shift control means 28 also incorporates a decoder 64 having data inputs 65 coupled to outputs of the priority circuit 62, a control input 66 coupled to the control unit 17 and an input 67 coupled to a shift direction trigger 68 having its input 69 coupled to the output 54 (Figure 2) of the shift direction generating AND gate 49. Inputs 70 (Figure 3) of the AND gates 60 are coupled to outputs 71 of the decoder 64 whose outputs 72 provide a multichannel output which is applied from the shift control means 28 to shift register 29.

The data masking unit 16 shown in Figure 4 comprises a mask code register 73 coupled to a decoder 74. Data inputs 75, 76 and a control input 77 of the mask code register 73 are used, respectively, as the inputs 23, 24, 25 of the data masking unit 16. Inputs 78, 79, 80, 81 of respective AND gates, 82, 83, 84, 85, are coupled to the outputs of the decoder 74. Outputs 86, 87, 88, 89 of the respective AND gates 82, 83, 84, 85, are coupled to the multichannel inputs 12, 14 (Figure 1) of the switches 9, 11, respectively.

Figure 5 illustrates the relative locations of a first operand 90 and a second operand 91 contained in the storage unit 1 (Figure 1). The first word of the second operand 91 (Figure 5) includes bytes 92, 93, 94, 95; note that bytes 92, 93, 94 do not apply to the second operand 91 being handled, but byte 95 does. The second word of the second operand 91 includes bytes 96,97,98,99, the three last words of that operand include bytes, 100, 101, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111. The word preceding the last but one word of the second operand 91 includes bytes 100, 101, 102, 103, and the last but one word of that operand includes bytes 104, 105, 106, 107 and the last word of the second operand 91 includes bytes 108, 109, 110, 111. The byte 108, applies to the second operand 91 being handled, while bytes 109, 110, 111 do not apply to this operand. The first word of the first operand 90 includes bytes 112, 113, 114,115; byte 112 does not apply to the first operand 90 being handled, while bytes 113,114, 115 do apply to it. The second word of the first operand 90 includes bytes 116, 117, 118,119, while the last but one and the last word include, respectively, bytes, 120, 121, 122,123 and bytes 124, 125, 126, 127. In the last word, bytes 124, 125, 126 apply to the first operand 90 and byte 127 does not apply to it.

The data field of the second operand 91 contains all bytes from the first byte 95 with byte code "I 1" to the byte 108, with byte code "00", inclusive. The data field of the first operand 90 contains all bytes from the first byte 113 with byte code "01" to the byte 126, with byte code "10", inclusive.

The above described processing device for variable length formats operates as follows.

It is known that an addressable unit of information available in a main store of a computer is a byte composed of a group of bits and followed by a check bit. A word in the main store is composed of four bytes, while a data field is allowed to start at and terminate in any byte within a given word. Full word operands are fetched from the main store; if an operand begins or terminates within the given word, the processor then receives both the bytes incorporated in the operand being handled and any bytes which do not apply to the operand.

A data field is defined either by the address of the first byte and the length of the field (the number of bytes in the field) of the first byte or by the addresses of the first and the last byte of the field. The concept represented by the term "byte address" is essential for any type of addressing. Tne byte address is composed of the word address of main storage and the byte location within the word (byte code) and is determined by: A=B+C where A is the byte address; B is the word address; and C is the byte code.

The practice is to ignore the byte code when a word is fetched from the main store.

The byte code may assume the binary values "00", "01", "10" and "I 1" which define, respectively, the first, second, third and fourth bytes of a word.

Prior to processing variable-length operands by full words, the operands must be arranged so that corresponding bytes occupy identical positions in the word, which means that the operands must be aligned. Most of the instructions used in modern computers specify only the addresses of the source operands, while the address of the result location is determined implicitly. As a rule, the result of an operation must be stored at the address of the first operand, namely, the result must be stored in the location of the first operand in main storage after processing is complete. Therefore, the second operand is usually aligned with respect to the first one, which enables the result to be automatically set in a position in which it should be transferred in main storage. The operands are aligned by shifting all bytes of the second operand to the right until the location of the rightmost byte of the second operand coincides with the location of the right-most byte of the first operand, provided the operands are right-aligned; the bytes are shifted in a similar manner to the left when the operands are left-aligned. The shift value is determined by the difference between the byte codes, while the shift direction is determined by mutual location of the bytes.

To determine the shift value and direction, the addresses of the rightmost bytes 108, 126 (Fig. 5) of the operands 90, 91, respectively, are fetched from the storage unit 1 (Fig. 1) and placed on the data exchange buses 4, 7. The inputs 31, 32 of the shift parameter forming means 27 of the data shift unit 26 are coupled to those wires of the data exchange buses 4, 7 through which the codes of the bytes 108, 126 (Fig. 5) are delivered during transfer of the addresses of the operands 90, 91 over the data exchange buses 4, 7 (Fig. 1), respectively. According to a signal delivered from the control unit 17 to the control input 30, the shift parameter forming means 27 produces and passes to the shift control means 28 shift parameters to determine the shift value and direction as shown in Table 1.

TABLE 1 Shift code Shift parameters Byte code on Byte code on data exchange data exchange Shift Shift bus 7 bus 4 value direction 00 00 0 00 01 8 to the right 00 10 16 to the right 00 11 24 to the right 01 00 8 to the left 01 01 0 01 10 8 to the right 01 11 16 to the right 10 00 16 to the left 10 01 8 to the left 10 10 0 10 11 8 to the right 11 00 24 totheleft 11 01 16 to the left 11 10 8 to the left 11 11 0 To align the second operand 91 (Fig. 5) with respect to the right boundary of the first operand 90, the second operand 91 is shifted 16 bit positions (two bytes) to the right. To this end, byte codes "00", "10" of the bytes 108, 126 respectively, are used to form shift code "0010" and corresponding shift parameters are therefore obtained according to Table 1.

During alignment, the words of the second operand 91 are fetched from main storage in succession and are loaded into the storage unit 1 through the device input 39 or 40 (Fig. 1) and through the data exchange bus 4 or 7. The current word available from main storage, along with the word obtained during the previous time step and stored in the storage unit 1, is placed on the data exchange buses 4, 7. According to a signal applied to the control input 38 of the storage unit I from the control unit 17, data is loaded and placed on the data exchange buses 4, 7 through the inputs 2, 5 and outputs 3, 6, respectively.

The last word of the second operand 91, composed of the bytes 108, 109, 110, 111 (Fig. 5), is moved from the storage unit 1 (Fig. 1) on the data exchange bus 7, while the last but one word of that operand, composed of the bytes 104, 105, 106, 107 (Fig. 5), is fetched from main storage and placed on the data exchange bus 4 (Fig. 1). Figure 6a illustrates the location of the two words on the data exchange buses 4, 7 from which they are delivered to the shift register 29.

According to the shift parameters available, the shift control means 28 is activated by a signal applied to its control input 33 from the control unit 17 to produce control signals which control the operation of the shift register 29. Two words of the second operand 91, composed of the bytes 104, 105, 106, 107, 108, 109, 110, 111 (Fig. 6a), are shifted 16 bit positions to the left, the bytes 110, 111 being moved off the shift register 29 (Fig. 1). As a result, the bytes 104, 105, 106, 107, 108, 109 are left in the shift register 29, while bytes 128, 129 containing zeros (Fig. 6b) are moved in from the left. The shifted last word, composed of the bytes 106, 107, 108, 109 (Fig. 6c) is loaded in the storage unit 1 via the output 37 (Fig. 1) of the shift register 29 and via the data exchange bus 7. In a similar manner, the shifted word, composed of the bytes 128, 129, 104, 105 (Fig. 6b), can be loaded, if necessary, in the storage unit 1 via the input 36 (Fig. 1) and the data exchange bus 4.

Now, the bytes 106, 107, 108 (Fig. 6c) of the last word of the second operand 91 (Fig. 5) to be processed occupy the identical positions, as compared to those of corresponding bytes 124, 125,126 of the last word of the first operand 90. At the same time, the next word, which is the word preceding the last but one word and composed of the bytes 100, 101, 102, 103 is called for and is placed together with the last but one word, previously fetched, (the bytes 104, 105, 106, 107) on the data exchange buses 4, 7 (Fig. 1), their mutual position being shown in (Fig. 6d). Then both words are shifted by the shift register 29 (Fig. 1) so that the bytes 102, 103, 104, 105 belonging to the second operand 91 (Fig. 5) are set in the identical positions as compared to those of the bytes 120, 121, 122, 123 of the last but one word of the first operand 90 (see Fig. 6e). The bytes 130 and 131 are moved in from the right and the last but one word shifted (the bytes 102, 103, 104, 105 shown in Fig. 6f) is then placed in the storage unit 1 (Fig. 1).

The described actions are performed repeatedly until the entire field of the second operand 91 (Fig. 5) is fetched from main storage, aligned with respect to the first operand 90 and placed in the storage unit 1 (Fig. 1). If the second operand 91 (Fig. 5) cannot be placed in the storage unit 1 (Fig. 1) completely, then the alignment is accomplished by parts.

With the second operand 91 (Fig. 5) aligned, the fetching of the first operand 90 from main storage is initiated in a word-by-word fashion. The first word of the first operand 90, composed of the bytes 124, 125, 126,127 (Fig. 5), is fetched from main storage and is passed via the device input 39 or 40 (Fig. 1) to the data exchange bus 4 or 7, for example, to the data exchange bus 4. Therefore, a respective word of the second operand 91 (Fig. 5), composed of the bytes 106, 107, 108, 109 (Fig. 6c), is transferred from the storage unit 1 to the data exchange bus 7.

The function according to which data is to be processed is determined by the control unit 17 (Fig. 1) which supplies a respective signal via the input 21 to the arithmetic/logic unit 20. The words composed of the bytes 124, 125, 126,127 (Fig.

5) and bytes 106, 107, 108, 109 (Fig. 6e) and belonging, respectively, to the first and second operands 90, 91 (Fig. 5) are delivered from the data exchange buses 4, 7 (Fig. I) and via the switches 9, 11 to the inputs 18, 19 of the arithmetic/logic unit 20 which performs appropriate operations. The processing result is written into the storage unit 1 through the input 22.

It should be noted that data relevant to the first and second operands 90, 91 (bytes 113, 114, 115, 124,125,126 and bytes 95, 96, 97, (Fig. 5, 6c) and 108 (Fig. 5), respectively is fetched from main storage together with data irrelevant to these operands (bytes 112, 127 and bytes 94 (Fig. 5, 6c) and 109 (Fig. 5), respectively).

To eliminate the irrelevant data, the data masking unit 16 produces a byte mask which is placed via the inputs 12, 14 on data delivered from the data exchange buses 4, 7 (Fig. I) to the switches 9, 11, respectively. The data masking unit 16 produces byte masks depending on byte codes passed from the data exchange buses 4, 7 to the inputs 23, 24 of the data masking unit 16 according to a signal from the control unit 17.

Table 2 lists mask types and classes. There are four mask classes. A respective mask code on the data exchange bus 7 is used to specify a mask class. The mask type within the mask class is defined by a respective byte code on the data exchange bus 4.

TABLE 2 Mask code Mask type (hexadecimal) Mask class on Byte code on data exchange data exchange bus7 bus4 00 00 FF FF FF FF 00 01 00 FF FF FF 00 10 00 00 FF FF 00 11 00 00 00 FF 01 00 FF 00 00 FF 01 01 FF FF 00 00 01 10 FF FF FF 00 01 11 FF FF FF FF 10 00 00 00 00 00 10 01 FF 00 00 00 10 10 FF FF 00 00 10 11 FF FF FF 00 11 00 FF FF FF FF 11 01 FF FF FF FF 11 10 FF FF FF FF 11 11 FF FF FF FF The class "00" mask is used to mask off data irrelevant to the given operand 90 (91) (Fig. 5) and located to the left (as viewed in the plane of the drawing) of the field of the operand being processed. The mask type is defined by the code of the leftmost byte 95 (113) of a respective operand 91 (90).

The class "01" mask is used to mask off data irrelevant to the given operand 90 (91) and located to the right (as viewed in the plane of the drawing) of the field of the operand being processed. The mask type is defined by the code of the rightmost byte 108 (126) of a respective operand.

The class "10" mask is used when two operands 91(90) of different length are aligned relative to their right boundaries (as viewed in the plane of drawing). This mask allows for the selection of the left portion of one operand 90 (91), which extends beyond the left boundary of the other operand 91 (90). The selected portion of the operand 91 (90) is then inspected for significance. The mask type is defined by the code of the leftmost byte 95 (113) of the shorter operand 90 (91).

The class "11" mask provides for the execution of an instruction according to the standard cycle. Byte masking involves other capabilities not shown in the above-described examples. This description is limited, however, to the application of the masks of classes "00" and "01" only.

When the address of the operand 90 (91) is transferred to main storage via the data exchange bus 4 (Fig. 1), then the code of a respective byte 95 (113) or 108 (118) (Fig. 5) is passed to the data masking unit 16 (Fig. 1) via the input 23. At the same time, the code of the mask class is placed on the data exchange bus 7 and is passed in the data masking unit 16 via the input 24. According to a signal from the control unit 17, which is delivered to the data masking unit 16 via the control input 25, the byte mask is generated which is then passed to the inputs 12, 14 of the switches 9, 11, respectively. The mask is placed on data moved through the data exchange buses 4, 7 according to respective signals available from the control unit 17. These signals applied to the inputs 13, 15 of the switches 9, 11, respectively, are generated at the moment the extreme words (bytes 94,95,96, 97 (Fig. 6c) and 113, 114, 115, 116 (Fig. 5) and bytes 106, 107, 108, 109 and 124, 125, 126, 127) of the operands 91, 90, respectively, are moved to the arithmetic/logic unit 20.

Thus, the data irrelevant to the operands 91, 90, which is obtained from main storage, is not involved in data processing.

The shift parameter forming means 27 of the invention (Fig. 2) operates as follows.

When the operands 90, 91 (Fig. 5) are fetched from main storage, their addresses available from the storage unit 1 (Fig. 1) appear on the data exchange buses 4, 7. The addresses of the extreme bytes 95, 113 and 108, 126 (Fig. 5) of respective operands 91, 90 are passed from the data exchange buses 4, 7 (Fig. 1) via the inputs 45, 46 (Fig. 2) to the shift code register 43. According to the byte codes and in the presence of a respective signal at the control input 47, available from the control unit 17 (Fig. 1), the shift code register 43 produces a four-bit shift code which is applied to the decoder 44 (Fig. 2). The signals from the output of the decoder 44 pass to the inputs 48, 50, 51 of the AND gates 49, 52, 53, respectively.

The shift direction generating AND gate 49 operates to gather shift direction conditions and its output 54 produces right and left shift signals. The shift value generating AND gates 52, 53 produce signals corresponding to the required shift values. When the operands 91, 90 (Fig. 5) are aligned, they should be shifted zero, eight, sixteen or twenty four bit positions. If no signals are present at the outputs 55, 56 of the AND gates 52, 53, a shift of zero bit positions takes place. A signal at the output of one of these AND gates corresponds to a shift of eight bit positions, while a signal at the output of the other AND gate corresponds to a shift of sixteen bit positions; finally, signals at the outputs of both the AND gates indicate that a shift of twenty four bit positions takes place.

The shift direction and values are calculated according to data shown in Table 1, relative to the operand 90 (91) (Fig. 5) whose address appears on the data exchange bus 4 (Fig. 1). In this case, the address of the operand being aligned (90 or 91, (Fig. 5) is placed on the data exchange bus 7 (Fig. 1). For example, the alignment relative to the first operand 90 (Fig. 5) requires that its address be placed on the data exchange bus 4 (Fig. 1) and the address of the second operand 91 (Fig. 5) be placed on the data exchange bus 7 (Fig. 1). In the case of right alignment, the addresses of the rightmost bytes 108, 118 of values are applied to the inputs 58 of the shift value triggers 57 to be stored therein. The number of the shift value triggers 57 is equal to the number of the shift values to be stored. Note that the latter also includes those shifts whose values do not coincide with the magnitudes 0, 8, 16 and 24 (for example, shifts by one, two, four and other similar bit positions). This is due to the fact that the shift control means 28 can handle not only variable length data but also other types of data. The stored shift values are delivered from the shift value triggers 57 to the inputs 63 of the priority circuit 62 which handles them according to the priority scheme available. If the shift value of higher priority is available, then the shift values of lower priority are not handled. The shift value, which is being handled according to the priority scheme at the given point in time, is delivered from the priority circuit 62 to one of the inputs 65 of the decoder 64. After the current shift value has been handled, a one output 71 of the decoder 64 produces a signal that is applied to the input 70 of the respective AND gate 60. In response to a signal available from the control unit 17 (Figure 1) and applied to the input 61 (Figure 3) of the AND gate 60, a reset signal is produced and passed to the input 59 of that shift value trigger 57 which stores the shift value handled a moment before, with the result that the trigger is reset. This provides for the possibility of handling the shift value of the next priority. According to the shift values stored in the shift value triggers 57 and to the shift direction stored in the shift direction triggers 68 and applied to the input 67 of the decoder 64, the control unit 17 produces signals passed to the control input 66 of the decoder 64 whose outputs 72 generate a sequence of control signals that are delivered to the shift register 29 (Figure 1).

The data masking unit 16 of the invention (Figure 4) operates as follows.

During transfer of the extreme words (bytes 92, 93, 94, 95, 108, 109, 110, 111 (Figure 5) and bytes 112, 113, 114, 115, 124, 125, 126, 127) of respective operands 91, 90, the mask code is placed on the data exchange bus 4 (Figure 1) and the address of the word being fetched is placed on the data exchange bus 7 (bytes 92, 93,94,95,108,109,110, 111 (Figure 5) and bytes 112, 113, 114, 115, 124, 125, 126, 127). The mask code is applied through the input 23 (Figure 1), and the code of the extreme byte 95, 108, 113, 126 (Figure 5) is applied through the input 24 (Figure 1) of the data masking unit 16, to the respective inputs 75, 76 (Figure 4) of the mask code register 73. In response to a signal applied to the control input 77 of the mask code register 73, the mask code is set in the latter and is then passed to the decoder 74. The outputs of the decoder 74 produce signals that are applied to the inputs 78, 79, 80, 81 of the AND gates 82, 83, 84, 85, respectively. The outputs of 86, 87, 88, 89 of these AND gates produce the required type of mask, according to Table 2, which is applied to data transferred via the data exchange buses 4, 7 (Figure 1).

The present invention provides for more effective production processes for the computer processor incorporating the invention and reduces its cost, since the processor features a more regular structure. This is attained due to the fact that the device of the invention is compatible with the processor structure oriented to full word data processing.

The invention also allows the units of the proposed device to be used for other types of data processing where full words are employed.

WHAT WE CLAIM IS: 1. Data processing apparatus for processing variable multibyte data fields, comprising a control unit arranged to control the actions of elements of the apparatus, a store arranged to store initial operands, intermediate results and the processing result at independent addresses, said store having a first input and a first output connected to a first data exchange bus, and a second input and a second output connected to a second data exchange bus and a third input connected to the output of an arithmetic-logic unit, each of said buses having an additional input and output; a data shift unit having a first data input and output and a first control input connected to the first data exchange bus, and a second data input and output and a second control input connected to the second data exchange bus, said data shift unit being arranged to effect shifting of the data supplied thereto from the data exchange buses in accordance with control data received through the control inputs; first and second data switches, connected respectively to the first and second data exchange buses, for supplying first and second inputs respectively of the arithmetic-logic unit with data from the respective data exchange buses and for masking the data according to signals from said control unit and a mask having a byte structure which is applied to each of said switches

**WARNING** end of DESC field may overlap start of CLMS **.

Claims (5)

1. **WARNING** start of CLMS field may overlap end of DESC **.

   values are applied to the inputs 58 of the shift value triggers 57 to be stored therein. The number of the shift value triggers 57 is equal to the number of the shift values to be stored. Note that the latter also includes those shifts whose values do not coincide with the magnitudes 0, 8, 16 and 24 (for example, shifts by one, two, four and other similar bit positions). This is due to the fact that the shift control means 28 can handle not only variable length data but also other types of data. The stored shift values are delivered from the shift value triggers 57 to the inputs 63 of the priority circuit 62 which handles them according to the priority scheme available. If the shift value of higher priority is available, then the shift values of lower priority are not handled. The shift value, which is being handled according to the priority scheme at the given point in time, is delivered from the priority circuit 62 to one of the inputs 65 of the decoder 64. After the current shift value has been handled, a one output 71 of the decoder 64 produces a signal that is applied to the input 70 of the respective AND gate 60. In response to a signal available from the control unit 17 (Figure 1) and applied to the input 61 (Figure 3) of the AND gate 60, a reset signal is produced and passed to the input 59 of that shift value trigger 57 which stores the shift value handled a moment before, with the result that the trigger is reset. This provides for the possibility of handling the shift value of the next priority. According to the shift values stored in the shift value triggers 57 and to the shift direction stored in the shift direction triggers 68 and applied to the input 67 of the decoder 64, the control unit 17 produces signals passed to the control input 66 of the decoder 64 whose outputs 72 generate a sequence of control signals that are delivered to the shift register 29 (Figure 1).

   The data masking unit 16 of the invention (Figure 4) operates as follows.

   During transfer of the extreme words (bytes 92, 93, 94, 95, 108, 109, 110, 111 (Figure 5) and bytes 112, 113, 114, 115, 124, 125, 126, 127) of respective operands 91, 90, the mask code is placed on the data exchange bus 4 (Figure 1) and the address of the word being fetched is placed on the data exchange bus 7 (bytes 92, 93,94,95,108,109,110, 111 (Figure 5) and bytes 112, 113, 114, 115, 124, 125, 126,

   127). The mask code is applied through the input 23 (Figure 1), and the code of the extreme byte 95, 108, 113, 126 (Figure 5) is applied through the input 24 (Figure 1) of the data masking unit 16, to the respective inputs 75, 76 (Figure 4) of the mask code register 73. In response to a signal applied to the control input 77 of the mask code register 73, the mask code is set in the latter and is then passed to the decoder 74. The outputs of the decoder 74 produce signals that are applied to the inputs 78, 79, 80, 81 of the AND gates 82, 83, 84, 85, respectively. The outputs of 86, 87, 88, 89 of these AND gates produce the required type of mask, according to Table 2, which is applied to data transferred via the data exchange buses 4, 7 (Figure 1).

   The present invention provides for more effective production processes for the computer processor incorporating the invention and reduces its cost, since the processor features a more regular structure. This is attained due to the fact that the device of the invention is compatible with the processor structure oriented to full word data processing.

   The invention also allows the units of the proposed device to be used for other types of data processing where full words are employed.

   WHAT WE CLAIM IS: 1. Data processing apparatus for processing variable multibyte data fields, comprising a control unit arranged to control the actions of elements of the apparatus, a store arranged to store initial operands, intermediate results and the processing result at independent addresses, said store having a first input and a first output connected to a first data exchange bus, and a second input and a second output connected to a second data exchange bus and a third input connected to the output of an arithmetic-logic unit, each of said buses having an additional input and output; a data shift unit having a first data input and output and a first control input connected to the first data exchange bus, and a second data input and output and a second control input connected to the second data exchange bus, said data shift unit being arranged to effect shifting of the data supplied thereto from the data exchange buses in accordance with control data received through the control inputs; first and second data switches, connected respectively to the first and second data exchange buses, for supplying first and second inputs respectively of the arithmetic-logic unit with data from the respective data exchange buses and for masking the data according to signals from said control unit and a mask having a byte structure which is applied to each of said switches

   from a data masking unit; said data masking unit having a first control input for selecting the mask class in accordance with data applied thereto from the first data exchange bus and a second control input for selecting the mask type within the selected class in accordance with data from the second data exchange bus so as to form and transmit to said first and second switches a mask serving to null unwanted bytes within data; said arithmetic-logic unit having its output connected to the store and performing arithmetic and logic operations on data applied thereto from said first and second switches; said data shift unit comprising a shift parameter forming means for producing signals denoting the value and direction of a required shift, said shift parameter forming means having a first data input for receiving data indicating the position within a word of a byte relative to which alignment is to be performed, said first data input being connected to the second data exchange bus by way of one of said control inputs of the data shift unit, said shift parameter forming means having a second data input for receiving data indicating the position of a byte which during the data shifting process must be shifted to the position indicated by the data received at said first data input, said second data input being connected to the first data exchange bus by way of the other of said control inputs of the data shift unit, data shift control means having its input connected to said shift parameter forming means and serving to produce control signals, denotive of the value and direction of a required shift, that are applied to a data shift register of a capacity of at least two words, said data shift register having a first data input, which is connected by way of said first data input of the data shift unit to the first data exchange bus, having a second data input which is connected by way of the second data input of said data shift unit to the second data exchange bus, and having a control input connected to the output of said data shift control means, said data shift register serving to shift the data supplied to it.
2. 2. Apparatus in accordance with claim 1 wherein said data shift parameter forming means comprising a data shift code register for storing the position within a word of a first byte relative to which alignment is to be effected, and the position of a second byte which must be shifted during the data shifting process, to the position of said first byte; a decoder connected to the output of said data shift code register and having a plurality of groups of outputs; a first coincidence circuit having inputs connected to a first of said groups of decoder outputs and providing an output denotive of the required direction of a data shift; a plurality of further coincidence circuits each of which has inputs connected to a respective group of said decoder outputs and yields a respective output denotive of a required value of said data shift.
3. 3. Apparatus in accordance with claim 2, wherein the data shift control means comprises a data shift direction trigger having its input connected to the output of said first coincidence circuit and a plurality of shift value triggers, equal in number to the number of possible values of data shifts each said shift value trigger having one input connected to an AND gate and another input connected to the output of a respective said further coincidence circuit; a priority circuit connected to the outputs of the data shift value triggers and a decoder having data inputs connected to the outputs of the priority circuit and of the data shift direction trigger, having a control input connected to an output of the control unit and having each of its outputs connected to a further input and a respective said AND gate.
4. 4. Apparatus in accordance with claim 1, 2 or 3 wherein the data masking unit comprises a mask code register having a first data input for selecting the mask class and connected to the first data exchange bus by way of said first control input of the data masking unit, having a second data input for selecting the type of mask within the selected class and connected to the second data exchange bus by way of said second control input of the data masking unit; a decoder connected to the output of the mask code register and a plurality of AND gates connected to respective sets of outputs of the decoder and serving to form byte masks in accordance with the selected class and type of mask and to apply said masks to said first and second switches.
5. 5. Data processing apparatus constructed and operating substantially as herein described with reference to the accompanying drawings.