JPH01147605A - Microprogram sequence controller - Google Patents

Abstract

PURPOSE:To simplify the constitution for reduction of the cost with a microprogram sequence controller by using a memory which stores the data showing the presence of absence of a break point in response to the address of a microinstruction. CONSTITUTION:A sequencer 3 produces the next address 4 of a microprogram memory 5 based on the microinstruction 2 received from a pipeline register 1. A memory 7 outputs the data 8 designated by an address 4 received from the sequencer 3. Then '1' is set at an area of the memory 7 corresponding to the address of the break point of the microinstruction 2. While '0' is set in the areas corresponding to other addresses respectively. A clock controller 9 sends a clock signal 11 to the sequencer 3 as a sequencer clock signal 12 by a start signal 10 and at the same time stops the output of the signal 12 by the signal 8 sent from the memory 7.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a microprogram sequence controller used in data processing devices and the like.

BACKGROUND OF THE INVENTION FIG. 2 shows a conventional microprogrammed sequence controller.

In FIG. 2, 21 is a pipeline register that holds the microinstruction being executed, and 28 is a sequencer that generates the next address 24 of the microprogram memory 25 based on the microinstruction 22 from the pipeline register 21. , the microprogram memory 25 outputs the next microinstruction 26 at this address 24.

27 is the address 2 of the microprogram that stops at -
Breakpoint setting register 29 holds 8;
Address 28 from breakpoint setting register 27
a comparator that compares the address 24 from the sequencer 24 described above and outputs a match signal 30 if they match;
A clock controller 31 outputs a clock signal 33 to the sequencer 23 in response to a start signal 82 and stops outputting the sequencer clock signal 34 in response to a match signal 30 from the comparator 29.

Next, the operation of the above conventional example will be explained.

In FIG. 2, when clock controller 31 is clocked by start signal 32, it outputs clock signal 33 as sequencer clock signal 34 to sequencer 23, and this microprogram sequence controller starts operating.

The sequencer 23 generates the next address 24 of the microprogram memory 25 based on the microinstruction 22 in the pipeline register 21, and when the microprogram memory 25 outputs the next microinstruction 26 at this address 24, the pipe Line register 21 holds this next microinstruction 26. Therefore, by repeating this operation, the microprogram is executed one after another.

During the sequential execution of this microprogram, the comparator 29 receives address 2 from the breakpoint setting register 27.
The clock controller 31 compares the address 24 from the sequencer 24 with the address 24 from the sequencer 24 described above, and outputs a match signal 30 if they match.
Stop the output of 4.

Therefore, in the conventional example, when the address 28 held by the breakpoint setting register 27 matches the address 24 of the currently executed microprogram, execution of that microprogram is stopped.

Problems to be Solved by the Invention However, in the above conventional microprogram sequence controller, the breakpoint setting register 2
When setting multiple breakpoints, the same number of breakpoint setting registers 27 Since the comparator 29 is required, there is a problem that the hardware is complicated and expensive.

Conversely, multiple breakpoint setting registers 27
A microprogram sequence controller provided with a comparator 29 and a comparator 29 has a problem in that the number of breakpoints that can be set is limited.

SUMMARY OF THE INVENTION In view of the problems of the prior art described above, it is an object of the present invention to provide a simple and inexpensive microprogram sequence controller in which the number of breakpoints to be set is not limited.

Means for Solving the Problems In order to solve the above problems, the present invention provides a memory for storing data indicating whether or not it is a breakpoint corresponding to the address of the microinstruction, and stores the microinstruction in the memory. The output of the clock signal is stopped when the address of the breakpoint is input and the data indicating the breakpoint is read.

Effect of the Invention With the above configuration, the present invention stores data indicating whether or not a breakpoint corresponds to the address of a microinstruction in the memory, so even when setting a plurality of breakpoints, the circuit does not have to be complicated and expensive. Therefore, it is possible to realize a simple and inexpensive microprogram sequence controller in which the number of breakpoints to be set is not limited.

EXAMPLES Hereinafter, the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram showing one embodiment of a microprogram sequence controller according to the present invention.

In FIG. 1, 1 is a pipeline register that holds the microinstruction being executed, and 3 is a microinstruction 2 from pipeline register 1.
The microprogram memory 5 outputs the next microinstruction 6 based on the address 4.

7 is a memory that outputs data (break pit) 8 specified by address 4 from sequencer 3;
In this memory 7, "1" is set in the area corresponding to the address of the break point of the microinstruction, and "0" is set in the area corresponding to other addresses.

9 outputs the cyclic clock signal 11 as a sequencer clock signal 12 to the sequencer 3 according to the start signal 10;
It is also a clock controller that stops outputting the sequencer clock signal 12 in response to the signal 8 from the memory 8.

Next, the operation of the embodiment according to the above configuration will be explained.

In FIG. 1, when the clock controller 9 is activated by the start signal 10, it outputs the clock signal 10 as a sequencer clock signal 11 to the sequencer 8,
This microprogram sequence controller starts operating.

The sequencer 3 generates the next address 4 of the microprogram memory 5 based on the microinstruction 2 from the pipeline register 1, and when the microprogram memory 5 outputs the next microinstruction 6 to this address 4, the pipe line register 1
holds this next microinstruction 6.

Therefore, by repeating this operation, the microprograms are executed sequentially.

During the sequential execution of this microprogram, address 4 of microprogram memory 5 is transferred to data 8 of memory 7.
(1 bit) is read out, and when data "1" is read out, the clock controller 31 stops outputting the sequencer clock signal 34.

Therefore, according to the above embodiment, in order to set "1" in the area of the memory 7 corresponding to the breakpoint address of the microinstruction in advance, the breakpoint setting register 27 and the comparator 29 of the conventional example
Plural breakpoints can be set simply by replacing .

As described in detail, the present invention provides a memory for storing data indicating whether or not it is a breakpoint corresponding to the address of a microinstruction, and inputs the address of the microinstruction into the memory to break. Since the output of the clock signal is stopped when the data indicating the point is read, the circuit does not have to be complicated or expensive even when setting multiple breakpoints. It is possible to realize a simple and inexpensive microprogram sequence controller with an unlimited number of controllers.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of a microprogram sequence controller according to the present invention, and FIG.
1 is a block diagram showing a conventional microprogram sequence controller; FIG. 1... Pipeline register, 8... Sequencer,
5... Micro program memory, 7... Memory for micro program break bit, 9... Clock controller. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
figure

Claims (1)

[Claims] a memory for storing data indicating whether or not a breakpoint corresponds to the address of the microinstruction; a sequencer for outputting the address of the microinstruction to the memory and reading the data; and outputting a clock signal to the sequencer; A microprogram sequence controller comprising: a clock controller that stops outputting a clock signal when data indicating a breakpoint is read from the memory.