JPS6249454A - Debug supporting circuit for microprogram - Google Patents

Abstract

PURPOSE:To confirm routine of an executed microprogram easily and surely by storing addresses of microinstruction read out from a control storage section and executed successively, and then analyzing them. CONSTITUTION:Microinstructions stored in a control storage section 2 are read out according to microinstruction addresses held in a microinstruction address register 1, and these are held in a microinstruction register 4, and the content of the microinstruction address register 1 is held in a copy register 3. When trace start command TST is executed by the microinstruction, a flip- flop 9 is set by output of a decoder 8, and a write permission signal ('1') is outputted to a trace memory 6. Consequently, the content of a trace register 3 is written in the trace memory 6. At the same time, a counter 5 is counted up by 1, and an address that determines write area of the trace memory 6 is advanced by 1. Thus, history of execution of microinstructions is stored in due order in the trace memory 6.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a microprogram debug support circuit in a data processing device or the like that uses microprograms.

TECHNICAL BACKGROUND OF THE INVENTION AND THE PROBLEMS J Conventionally, it has become difficult to completely debug microprograms in this type of data processing device as microprograms become more complex and more demanding. For example, in order to process a certain function, a microprogram branches into several branches according to input conditions and performs the above processing.

By the way, conventionally, this type of debugging is performed by executing microinstructions one step at a time and visually checking the progress by some means, so it is difficult to execute all branched routines while debugging a complex microprogram as described above. It has been difficult to confirm whether or not this has been done because it is inefficient and there are often oversights.

[Object of the Invention] In view of the above-mentioned drawbacks, an object of the present invention is to provide a microprogram debugging support circuit that allows easy confirmation of executed microprogram routines.

[Summary of the Invention] The present invention achieves the above object by sequentially storing addresses of microinstructions read from a control storage unit and executed, and later analyzing the addresses.

[Embodiment of the Invention] An embodiment of the present invention will be described below with reference to the drawings. 1st
The figure is a block diagram showing an embodiment of the microprogram debugging support circuit of the present invention.

Reference numeral 1 is a microinstruction address register that holds the address of a read microinstruction, and reference numeral 2 is a control storage section that stores a microprogram (microinstruction). Reference numeral 3 is a copy register that copies the contents of the microinstruction address register 1, and reference numeral @4 is a microinstruction register that temporarily holds the microinstruction read out from the control storage section 2. Reference numeral 5 is a counter that counts up one by one, and reference numeral 6 is a trace memory that sequentially stores the contents of the copy register 3. Code 7 is below the command held in microinstruction register 4 (described later)
8 is a decoder that decodes the command TST/TSP (described later) held in the same register 4, and 9 is a TS sent from decoder 8
The flip-flop 10, which is set by the T command and reset by the TSP command, performs an AND condition between the output from the decoder 7 and the output from the flip-flop 9, and sends the result to the trace memory 6 as a write permission signal to enable counting up. This is a logic gate that outputs a signal to the counter 5.

FIG. 2 shows the format of the n-bit wide microinstruction prepared in the present invention and held in the microinstruction register 4 of FIG. 1. In the figure, T indicates a trace permission command, TST indicates a trace start command, and TSP indicates a trace stop command.

Next, the operation of this embodiment will be explained. micro instructions,
According to the microinstruction address held in the address register 1, the microinstruction stored in the control storage section 2 is read out and held in the microinstruction register 4. In synchronization with the above operation, the contents of the microinstruction address register 1 are held in the copy register 3. next,
When the trace start command TST is executed using the microinstruction held in the microinstruction register 4, the decoder 8
The flip-flop 9 is set by the output. Thereafter, when the trace enable command T is specified by a microinstruction read from the control storage unit 2 and executed, the output of the decoder 7 becomes true (“1”) and is set as described above. The output of flip-flop 9 is true (
“1''), so the AND circuit 1 that inputs these
The AND condition of 0 is established, and a write permission signal (“1”) is output to the trace memory 6. Therefore, the contents of the copy register 3 are written to the trace memory 6.

At the same time, a count up permission signal (1'') is output from the AND circuit 10 to the counter 5, and this counter 5
is counted up by 1, and the address that determines the write area of the trace memory 6 is advanced by one. Incidentally, an initial value can be set for the counter 5 at the time of system initialization or by other commands, which will not be explained here.

Next, use the trace stop command TSP with another microinstruction.
When this is executed, the flip-flop 9 is reset by the output of the decoder 8, and the output of this flip-flop 9 is made false (""O"). Therefore, the AND condition of the AND circuit 10 cannot be satisfied, and the write permission signal and count-up The permission signal is no longer output, and the operations of the counter 5 and trace memory 6 are stopped. The above operations are repeated, and the execution history (address of the executed microinstruction) of the microinstruction in which the trace enable command inserted into the microprogram in advance is written is sequentially stored in the trace memory 6. By executing the start and stop commands TST and TSP before and after the microprogram routine to be traced, the execution history of only the desired routine can be stored in the trace memory 6.

According to this embodiment, the contents of the trace memory 6 are logged out to the main memory (not shown), and the contents of the microprogram are analyzed by analyzing the executed microinstructions and the addresses of the routines of the microprogram. The execution process can be easily and reliably understood.

Effects of the Invention J As described above, according to the microprogram debugging support circuit of the present invention, the addresses of microinstructions read out from the control storage unit and executed are sequentially allocated, and later analyzed. This has the effect that the routine of the executed microprogram can be easily and reliably confirmed.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of a microprogram debugging support circuit of the present invention, and FIG. 2 is a diagram showing an example of the format of a microinstruction stored in the microinstruction register of FIG. 1. DESCRIPTION OF SYMBOLS 1... Micro instruction address register, 2... Control storage unit, 3... Copy register, 4... Micro instruction register, 5... Counter, 6... Trace memory, 7.8...・Decoder, 9...Flip-flop agent Patent attorney Book 1) Takashi Figure 1 Figure 2

Claims (1)

[Claims] A microprogram data processing device includes: a control storage unit that stores microinstructions to which a trace permission command, a trace start command, and a trace stop command are added in advance; a storage unit that sequentially stores addresses of executed microinstructions; and a trace permission unit. A microprogram debugging support circuit comprising write control means for writing the address of the microinstruction into the storage means using a trace start command and stopping the write operation using a trace stop command after execution of the command. .