JPS5854469A - Multiplexing system of computer - Google Patents

Abstract

PURPOSE:To increase a processing speed for a multiplexing system of computer, by using plural computers having the same control procedures to a control subject. CONSTITUTION:The computers 9, 10 and 11 having the same control procedures are used to a control subject 1. The start signals 9A, 10A and 11A are applied to the computers 9, 10 and 11 respectively. Thus these computers start a process respectively. An output switch timing control part 4 produces switch signals 6A-8A from a clock pulse 3A and the process end signal. Receiving these switch signals, the output switch parts 6-8 open their gates to feed the outputs of the computers 9-11 with which the process is over to a common output part 2. The part 2 delivers the processed data to the subject 1. In such way, the processing speed is increased for a multiplexing system of a computer.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a multiplexed system C of nine combinators having a plurality of identical control procedures for two identical control objects.

In the general control system 62 using a computer, one combiator is used for the control object 1 and (2) as shown in 1g-2.

In conventional control systems, there is only one computer to control the object, so the control speed is determined by the processing power of one combiator. If you don't prepare a comviator,
There is a drawback that it does not work.

The present invention has been developed to eliminate the above-mentioned drawbacks, and it is possible to perform faster control (2) it is possible to perform high-speed control without preparing a faster computer. It is an object of the present invention to provide a computer multiplexing system with a plurality of identical control procedures for two.

The present invention will be described below with reference to an embodiment shown in FIG. 11 and a time chart shown in FIG.
Enter 1. Timing control unit 4 outputs system clock pulse 3 from system clock generator g3
and distributed to the computer startup timing control section 5.

The computer start-up timing control section 5 generates start-up signals 9, 10, and 11 as shown in Figure 3 to sequentially start up each computer 9, 10, and 11. Each computer starts geography by the activation signal received from the computer start-up control unit (9m e 10 As 11m), and when the processing is completed, sends the output to the output switching unit 6.7.8, and sends the geography completion signal. 9B.

The output switching tie control unit 4 outputs 10B#11B to the output switching tie control unit 4, and outputs the system clock pulse 3, the processing completion signal 9Be, IOB, IIB switching signals 6, 7, and 8. The output switching unit 697t8 opens the gate and receives the switching signal 6m*748m, which is applied to the output switching unit 6,7゜8 corresponding to the computer 9.10.11 which has completed the processing. After the processing is completed, the common output section 2 inputs the output of the computers 9, 10. It is possible to increase the processing speed as a writing system without increasing the total geographical speed of the computer. ・In Figures 2 and 3, three computers were used to explain nine systems, but any number of computers may be used.

As explained above, (1) the invention (2) uses a system that can perform faster control than C2 without increasing computer processing speed; Control, trajectory calculation, etc. can be considered.

[Brief explanation of drawings]

FIG. 1 is a conventional configuration diagram, FIG. 2 is a configuration diagram showing an embodiment of the present invention, and FIG. 3 is a timing chart showing the timing of each part making up the configuration of the present invention. Controlled object 2...Common output part input signal l...Computer 2...Common output part 3...
- System clock pulse 39.・System clock generation section 6L... Switching signal (1) 4... Output switching timing control i11 section 7A... Switching signal (2) 5... Computer startup timing control section 8A... Switching signal (3) 6 ... Output switching section (1) S#^... Starting signal (1) 7... Output switching section (2) 10A... Starting signal (2) 8... Output switching section (3) 11m ...Start signal (3) 9...Computer (1) 9...Processing completion signal (1) 10-...Computer (2) 10B
...II & processing completion signal (2) 11...computer (3) 11B...processing completion signal (3) (7317) Representative Patent Attorney Noriyuki Chika 01
or 1 person) Figure 1

Claims (1)

[Claims] A plurality of combiators having the same control procedure and sharing the load from the controlled object, a switching unit for switching and outputting the outputs of these combiators, and a computer-starting tie construction control for controlling the starting timing of the combiators. A multiplexed combinator system characterized by comprising: an output switching tie controller that controls the switching timing of the switching unit; and a system clock generator that generates a control tie for the entire system.