JPH0277930U

JPH0277930U -

Info

Publication number: JPH0277930U
Application number: JP15645288U
Authority: JP
Priority date: 1988-11-30
Filing date: 1988-11-30
Publication date: 1990-06-14

Description

[Brief explanation of drawings]

第１図は本考案の実施例に係る多数決判別回路
のブロツク図、第２図は本考案の原理を説明する
ための図、第３図は従来の多数決判別回路のブロ
ツク図である。１，２１；データ入力線、２，２２；切換器、
３，６，２３乃至２５，２９；メモリ、４；ＥＸ
―ＯＲゲート、５；スイツチ、７；インバータ、
８，９；ＡＮＤゲート、１０；ＯＲゲート、１１
，３０；データ出力線、１２，３１；制御回路、
２６_１乃至２６_ｎ；加算器、２７_１乃至２７_ｎ；
振分器、２８；基準値発生器。 FIG. 1 is a block diagram of a majority decision circuit according to an embodiment of the present invention, FIG. 2 is a diagram for explaining the principle of the present invention, and FIG. 3 is a block diagram of a conventional majority decision circuit. 1, 21; data input line, 2, 22; switch,
3, 6, 23 to 25, 29; memory, 4; EX
-OR gate, 5; switch, 7; inverter,
8, 9; AND gate, 10; OR gate, 11
, 30; data output line, 12, 31; control circuit,
26 ₁ to 26 _n ; Adder, 27 ₁ to 27 _n ;
Sorter, 28; reference value generator.

Claims

[Scope of utility model registration request]

Three groups of digital data transmitted in series are sequentially input, and the first digital data is sent to the first terminal.
a switch that distributes second digital data to a second terminal and third digital data to a third terminal; and a first memory that sequentially stores the first digital data distributed to the first terminal. and an exclusive OR circuit which sequentially inputs the output of the first memory and the second digital data distributed to the second terminal and outputs the exclusive OR of both, and this exclusive OR circuit. a second memory that sequentially stores the outputs of the sum circuit; and if the value stored in this second memory indicates that all bits of the first digital data and the second digital data match; , a control circuit that immediately outputs the first digital data stored in the first memory; and a control circuit that immediately outputs the first digital data stored in the first memory;
If all bits of the memory do not match, select the data stored in the first memory as a matching output among the outputs from the second memory;
A majority determination circuit comprising: a gate circuit that selects third digital data distributed to the third terminal based on a non-coincidence output.