JPH0548581A - Method for parity attachment - Google Patents

Abstract

PURPOSE:To make the parity calculating result of parity attaching circuit that is treated as spare by redundancy constitution coincide with the parity calculating result of parity attaching circuit that is treated as existing with redundancy constitution by installing a matching circuit. CONSTITUTION:Input data is inputted in both parity attaching circuit (A)2 and parity attaching circuit (B)3, the output from each of attaching circuit 2 and 3 is selected by selecting circuit 4 in accordance with selecting signal 5, and the result is output as output data 6. Here, when the selecting signal 5 is 'L', the output from attaching circuit (A) 2 is selected, and when the selecting signal 5 indicates 'H', the output from attaching circuit (B) 3 is selected. Accordingly, by sending the output from matching circuit 7 to attaching circuits A(2) and (B)3 in accordance with the selecting signal 5, the parity calculating results of parity attaching circuits are made to coincide with each other.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a parity adding circuit, and more particularly to a parity adding system when a plurality of parity circuits are used in a redundant configuration.

[0002]

2. Description of the Related Art In a conventional parity adding circuit, each parity adding circuit operates independently when used in a redundant configuration.

FIG. 2 is a block diagram showing an example of a two-circuit configuration of a conventional parity adding circuit.

In FIG. 2, input data 8 is input to a parity addition circuit (A) 9 and a parity addition circuit (B) 10, and the output of each parity addition circuit is a selection circuit 11.
Output data 1 selected according to the selection signal 12 in
It is output as 3.

[0005]

In the conventional parity adding circuit, when used in a redundant configuration, each parity adding circuit operates independently. Therefore, when the parity calculation initial values are different, There is a problem that the parity check circuit detects a parity error when the parity calculation result of each parity addition circuit is different and the redundancy addition circuit is switched.

The present invention has been made in view of the above-mentioned conventional circumstances, and therefore an object of the present invention is to provide a novel parity addition system capable of solving the above problems inherent in the conventional art. Especially.

[0007]

In order to achieve the above object, the parity addition method according to the present invention is such that a parity calculation result of a spare parity addition circuit in a redundant configuration is used in a parity addition circuit that is currently used in a redundant configuration. It is configured with a matching circuit that matches the parity calculation result.

[0008]

BEST MODE FOR CARRYING OUT THE INVENTION The present invention will now be described in detail with reference to the accompanying drawings with reference to the accompanying drawings.

FIG. 1 is a block diagram showing an embodiment of a two-circuit configuration of a parity adding circuit using the parity adding method according to the present invention.

Referring to FIG. 1, an input data 1 is input to a parity adding circuit (A) 2 and a parity adding circuit (B) 3, and outputs of the parity adding circuits 2 and 3 are selected by a selecting circuit 4. It is selected according to the selection signal 5 and output as output data 6. In this circuit, the output signal of the parity addition circuit (A) 2 is selected when the selection signal 5 is "L", and the output of the parity addition circuit (B) 3 is selected when the selection signal 5 is "H". And

By sending the parity according to the selection signal 5 from the matching circuit 7 to the parity adding circuit (A) 2 and the parity adding circuit (B) 3, the parity calculation results of the parity adding circuits are matched.

FIG. 3 shows a frame structure of data, and shows that the parity calculation result of the previous frame is inserted at the parity position of the current frame.

FIG. 4 is a concrete block diagram of a 1-parity adding circuit of the 2-circuit structure parity-adding circuit.

Referring to FIG. 4, the data selector 14
Selects the input data 15 and the parity data 16 according to the parity pulse 17 and outputs them as output data 18. In this circuit, the parity data 16 is selected when the parity pulse 17 is "H", and the input data is selected when the parity pulse 17 is "L".

The data latch 19 latches the output data 18 for each data pulse 20, and the parity calculator 21 calculates the parity of the latched data. Since the parity is calculated for each frame as shown in FIG. 3, the frame pulse 2
Reset with 2.

The parity selector 23 selects the output of the parity calculator 21 or the parity data 25 of the matching circuit 7 according to the selection signal 24 of the matching circuit 7. In this circuit, the parity data 25 of the matching circuit is selected when the selection signal 24 of the matching circuit is "H", and the output of the parity calculator 21 is selected when it is "L". Matching circuit 7
It is possible to match the parity calculation result of this parity addition circuit with the parity calculation result of another parity addition circuit by selecting the parity data 25 of.

The parity latch 26 receives the frame pulse 2
The output of the parity selector 23 is latched every 2 and the parity data 16 is output.

FIG. 5 shows the timing of the parity addition circuit of FIG.

In FIG. 5, according to the frame structure 27, the data pulse 28 is a frame pulse 2 for each data.
9 forms the head pulse of the frame for each frame, and the parity pulse 30 becomes "H" at the timing of parity.

FIG. 6 is a block diagram showing a specific structure of the coincidence circuit 7.

Referring to FIG. 6, the parity selector 31
Selects the parity data 32 of the parity addition circuit (A) 2 and the parity data 33 of the parity addition circuit (B) 3 according to the selection signal 5, and outputs the parity data 34 of the coincidence circuit 7.

In this circuit, the parity data 32 of the parity addition circuit (A) 2 is selected when the selection signal 5 is "L", and the parity data of the parity addition circuit (B) 3 is selected when the selection signal 5 is "H". It shall be.

The selection signal generator 35 generates a selection signal 36 for the matching circuit 7 for the parity addition circuit (A) 2 and a selection signal 37 for the matching circuit 7 for the parity addition circuit (B) 3.

[0024]

As described above, according to the parity addition method of the present invention, the parity calculation result of the parity addition circuit which is a spare in the redundant configuration is used as the parity in the redundant configuration because the matching circuit is provided. The parity calculation results of the additional circuits can be matched.

[Brief description of drawings]

FIG. 1 is a block configuration diagram showing an embodiment of a two-circuit configuration of a parity adding circuit using a parity adding circuit of the present invention.

FIG. 2 is a block diagram of a two-circuit configuration of a conventional parity adding circuit.

FIG. 3 is a diagram showing a frame structure of data.

FIG. 4 is a block diagram showing a specific example of a parity adding circuit.

FIG. 5 is a timing diagram of a parity adding circuit.

FIG. 6 is a block diagram showing a specific example of a matching circuit.

[Explanation of symbols]

 1 ... Input data 2 ... Parity adding circuit A 3 ... Parity adding circuit B 4 ... Selection circuit 5 ... Selection signal 6 ... Output data 7 ... Matching circuit 8 ... Input data 9 ... Parity adding circuit A 10 ... Parity adding circuit B 11 ... Selection circuit 12 ... Selection signal 13 ... Output data 14 ... Data selector 15 ... Input data 16 ... Parity data 17 ... Parity pulse 18 ... Output data 19 ... Data latch 20 ... Data pulse 21 ... Parity calculator 22 ... Frame pulse 23 ... Parity Selector 24 ... Matching circuit selection signal 25 ... Matching circuit parity data 26 ... Parity latch 27 ... Frame configuration 28 ... Data pulse 29 ... Frame pulse 30 ... Parity pulse 31 ... Parity selector 32 ... Parity data of parity addition circuit A 33 … Parity addition circuit B Paris I de - data 34 ... Paritide matching circuit - motor 35 ... coincidence circuit of the selection signal to the selection signal 37 ... parity adding circuit B of the coincidence circuit to selection signal generator 36 ... parity adding circuit A

Claims (1)

[Claims] 1. A redundant configuration parity adding circuit using a plurality of parity adding circuits for performing a parity calculation in units of frames of an arbitrary length and adding a parity calculation result to the next frame for which a calculation is performed is redundant in a redundant configuration. A parity addition method characterized by comprising a matching circuit for matching the parity calculation result of the parity addition circuit with the parity calculation result of the current parity addition circuit in a redundant configuration.