JPS6167322A - Error correction memory controlling circuit of reed solomon encoding/decoding system - Google Patents

Abstract

PURPOSE:To generate the address of an error correcting memory in accordance with Reed Solomon codes, by combining outputs of a down counter which reduces a specific value and an up counter which outputs a control signal when counts a prescribed value. CONSTITUTION:When a start pulse Q is inputted, a down counter (DC)10 is set to a loaded condition and an UP counter (UC)20 and the DC10 are reset by outputs of FFs 31 and 32, respectively. The code length 32 of a Reed Solomon (C1) code which is a set count value D is set in the DC10 and, at the same time, a clock CLK is counted and, thereafter, the set value D is successively reduced. Simultaneously, the UC20 counts the clock CLK and, when a count value is the C1 code length 32, outputs a control signal 20a. When the count value is another C2 code length 38, the UC20 outputs a nother control signal 20b to a selection circuit 30. The circuit 30 outputs a selecting signal 30a at either one of selecting signals S and R of the C1 and C2 codes and clears the DC10 and UC20 through the FFs 31 and 32, and then, outputs an address signal corresponding to the C1 or C2 code in accordance with the clock CLK number 32 or 28.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention includes interleaving of two Reed-Solomon codes.
An error correction circuit Vct4A is used in the decoding method of the doubly combined cross-interleaved code.

[Traditional technique]

In digital sound Q1 equipment etc., two Lead-on-Romon codes? Interleap? Combine them twice. For example, for compact discs, the CIRC method is called C2 (2
8,24) code and C1 (32,28) code. Here, the 11th ji in parentheses is the code length, '4'r 2 songs indicate the total number of information symbols, and 8 bits is one symbol. Therefore, when decoding, the C1 code is decoded by the 01 decoder, and the C2 code is read by the C2 decoder. Further CIRC
In this method, delays and rearrangements are added before and after.

Since this is a cumbersome process, the circuit scale is large,
The calculations were also complicated. Therefore, processing that uses memory, such as delay, taint-leave, and replacement, is performed on one main memory to prevent the circuit scale from increasing. Therefore, as a circuit that performs correction according to the above formula, a circuit like the one shown in Figure 3 is suitable.In addition to the main memory 3 that stores data, this circuit temporarily stores all data. A correction memory 2 is provided, and the data is once transferred to the correction memory 2 through the entire iD type 2 flip-flop 7, and then again transferred from the correction memory 2 to the king memory 5 via the D type flip 70 and the knob 8. At this time, error correction is performed by adding the error pattern with data in the exclusive OR circuit 6.Q In the above circuit, in order to perform error correction, the correction memory 2 stores Vc data and Since the timing at which data is sent from the correction memory 2 for error correction is determined by the CLKI that drives the address counter of the correction memory 2, timing adjustment is easy.

[Problem that the invention seeks to solve]

An object of the present invention is to create an address signal in accordance with each of the C1 code and C2 code in order to control the data loading and sending of the correction memory 2 in the circuit shown in FIG. It is about providing.

[Means to solve all problems]

Does the circuit of the present invention have a clock input? A down counter that outputs a count +i that is common and gradually decreases from a predetermined count value, and an amplifier counter with a decoder that generates all control signals when the count lit reaches the code length of the C1 code and C2 code. The output of the down counter, one bit of the selection signal, and the entire set are selected by means for selecting 1 of the control signal of the up counter according to the selection signal of the C1 code/C2 code and clearing the image counter. At the same time, by sending it as an address signal of the correction memory, the correction memo IJ'
It is intended to be controlled.

[For production]

The operation of the circuit of the present invention will be explained in detail in Examples, but will be briefly explained below. Since the code length of the C1 code is 62 symbols, the down counter is first set to '32'.
Load it into . Then, the count value is completely decreased one after another, and the count value is sent to the correction memory as an address signal. As a result, data from the king memory is delivered to address numbers 62.31, . . . . If this address number corresponds to the symbol position within the frame, the symbol ++ 3
11+ will be stored at address "32°". At the same time, the up counter counts up from 1°01', and when it counts up at 32''-i, it generates a control signal and clears both counters.In the case of C2 code, it is a 1'1t2B symbol, so the down counter It is good to load "28" first (・The above explanation is for the case of importing data from the king memory, but when sending data to the king memory, the check symbol is dropped in the C1 code and the symbol is set as 28. All you have to do is send it out, so first load the down counter to "28".

〔Example〕

Hereinafter, a VC according to an embodiment of the present invention will be described with reference to the circuit block diagram of FIG. 1 and the time chart of FIG. 2.

In FIG. 1, a down counter 10. Up counter 20 uses common clock CLKff count through 0°
When the “0” start pulse (Q) is input, this “0” signal is the load signal of the down counter 10 and (JK) the output FLO of the flip-flop 31.
1 (R8) flip-flop 62
The output of FLO2'ft is set to 0''. Down collar/ri 1
0 is a-do borrowed number, the initial count is set to 1, and the entire load is completed. When the clear terminal of down counter 1G is high 1°,
It is reset, but since the key is 0°, it can be loaded. When the start pulse [Q] disappears, the down counter 10 sequentially counts down from the set count value and outputs the entire output as the signal C42. The data is sent to the address bus of the correction memory 2.For example, when reading data into the correction memory 2 as part of the C1 decoder operation, the set count value is set to 32'' and the address ``52'' is sent.
” The data will be read from .

By the way, since the start pulse (c+:IU(Jll free lag 5 output FLOOi'' is set to 1'), the clearing of the up counter 20 is canceled and the up counter 20 counts the clock CLKi.The up counter 20 counts as the decoder output. When the number is 32'', the control signal 20a is fully output, and when the number is '28'', the control signal 20b is fully output. Both are 10' and are selected by the selection circuit 60 by the selection key (S, R) of the C1°C2 code. Output as a signal of 30m and input manually to the clear terminal and S terminal of flip 70 and 31 and 32, respectively. (JK) flip 7
The output FLOO of the 0 toggle 61 becomes IIQI+, and the up counter 20 becomes a clear state, and the output Fl, 02 #i"1" of the (BS) flip 70 toggle 32 becomes the down counter 10, and the down counter 10 becomes a clear state.

In the case of C1 code, the selection signal tit (S=1. R=0
), when the C2 code is selected, the selection signal is (S=0.R=1), so the signal 30a is the clock number "32" when the C1 code is used.
', and in the case of C2 code, it appears with the clock number "28".

As described above, the C1 code is placed on the address bus.

In each case of the C2 code, data is transferred from the king memory 3 to the predetermined address of the correction memory as shown in Fig. 3 by the corresponding address signal.◎ In the time chart shown in Fig. 2 , signals C43 and C44 indicate signals on the data bus, and as shown in FIG. The set count value of the down counter 10 is 28'' in the C1 code when all the ratio data stored from the correction memory 8 is output. C
2 code, it may be set to 24''', because all error correction is performed only on the information symbol.

Note that the above down counter 10 is used as an address signal.
1 bit of the CI, C2 selection signal is output to the output C42 of the
By adding this as fMsB (R pit), the correction a of the CI decoder and C2 decoder can all be performed in a time-division manner in the same circuit.

〔Effect of the invention〕

As explained above (7), according to the present invention, when data stored in the main memory is transferred to the correction memory or transferred in the reverse direction, the correction memory can be directly driven. , it is possible to ensure that each symbol position during error correction operation is in the same rectangle.Therefore, there is no possibility of error correction occurring.Correction operation f'F of the C1 decoder and C2 decoder: All must be performed in the same (b) path. It's loud.

The signal line FLOO indicates that the authentication memory is in an operating state.
It can be found by FLO2 and used as a flag,
Can be used to connect the decoder to other processing steps.

[Brief explanation of drawings]

FIG. 1 is a circuit block diagram of an embodiment of the present invention, FIG. 2 is a time chart, and FIG. 3 is an explanatory diagram of a system for correcting code errors using a correction memory controlled by the present invention. be. 2... Correction memory, 3... King memory, 7.
8... D-type flip 70 tubes, 10... Down counter, 20... Up counter, 30... (CI, C2) selection circuit, 3
1... (JK) Flip Flor Rough-32...CBS
) Flip-flop, S, R...CI, C2 code selection signal, 20*, 20b...control signal.

Claims (1)

[Claims] When decoding the C1 code and C2 code of the Reed-Solomon code, a correction memory for temporarily storing data is provided in addition to the main memory for storing data, and data is transferred between the two memories. It is a circuit that controls a correction memory that performs error correction when the error is corrected, and includes a down counter that uses a common clock input and outputs a count value that decreases sequentially from a predetermined count value, and a down counter that outputs a count value that decreases sequentially from a predetermined count value, and a down counter that outputs a count value that is sequentially decreased from a predetermined count value. an up-counter with a decoder that generates a control signal when the code length becomes equal to the code length of the up-counter, and means for selecting 1 of the control signal of the up-counter based on the C1 code/C2 code selection signal and clearing both the counters. A correction memory control circuit using a Reed-Solomon code/decoding system, characterized in that the output of the down counter and one bit of the selection signal are combined and sent as an address signal for the correction memory.