JPS63128820A - Memory type interleave circuit - Google Patents

Abstract

PURPOSE:To decrease the circuit scale by using a mode changeover signal so as to switch an output of an address counter in a memory type interleave circuit thereby using an address counter for write/read in common. CONSTITUTION:A burst error of a communication system and a computer system is written in a memory in row direction and read from a column direction, interleaved and randomized by the complete block system. The high/low order bits of the addresses accessing the memory are counted by high/low order address counters 7, 8 and switched by an address switching circuit in response to a Q output of a FF of a mode switching circuit 9 set/reset in response to a write/read start signal to form a write row address signal and a column address signal. Thus, the address counter is used in common for the write/read, it is not required to provide two sets of exclusive counters and the circuit scale is decreased.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a memory-type interleaving circuit that randomizes burst errors caused by concentration of mark@ errors, and particularly to a memory-type interleaving circuit for dealing with burst errors in data transmission. It is connected to a metric interleaving circuit.

[Conventional technology]

Error correction codes are generally used to correct data errors in communication systems and computer systems. In actual communication lines, many burst errors occur. Errors in computer memory are also burst errors.

In order to correct such burst errors, even if an error correction code is directly applied, the correction effect is small, so a method is used in which an interleave circuit is used to randomize the burst errors.

One of these interleaving methods is a complete block method. As shown in FIG. 2(A), input data is written in the row direction and read out in the column direction.

Conventionally, this type of complete block interleaving circuit has a storage section (hereinafter referred to as memory) that stores data, a write address counter that generates a write address for the memory, and a read address that generates a read address. It consisted of a read address counter.

[Problem that the invention seeks to solve]

The conventional complete block interleaving circuit described above has two address counters, one for writing and one for reading, so the circuit scale becomes large and it is necessary to use an encoder and decoder that can correct short burst errors. However, there is a disadvantage that the advantage of being able to reduce the circuit scale of the entire error correction circuit is lost due to the combined use of the inter 9 to 1 circuits.

An object of the present invention is to reduce the circuit scale by switching the output of the address counter using a mode (write/read) switching signal so that the old address counter and the 7-dress counter for reading can be shared. be.

[Means for solving problems]

The memory type interleaving circuit of the present invention includes a memory, a counter for an E-order address and a counter for a lower address that generate the address signal of the memory, and a counter that generates the generated upper address signal and lower address signal. It includes an address switching circuit that switches to a row address signal or a column address signal of the memory, and a mode switching circuit that switches the address switching circuit to a write mode or a read mode.

[Effect]

Therefore, the present invention makes it possible to share the write address counter and the read address counter by switching the outputs of the upper and lower address counters using a mode (write/read) switching signal, thereby creating an interleaved circuit with a small circuit scale. be able to.

(Example) The present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention, and FIG.
(^) in the figure is a diagram explaining the complete block interleaving method, and (B) in FIG. 2 is an explanatory diagram showing address state transition. Clock switching circuit 10 on the left side of Fig. 1
has an input terminal 3 for the write clock WC and an input terminal 'f-4 for the read clock rc of the memory (not shown), and its output terminal f is the clock terminal of the counter 7 of the upper address and the counter 8 of the lower address. connected to ck. The respective outputs iPQ of the upper address counter 7 and the lower address counter 8 are connected to an address switching circuit 12.

The address signal input to the address switching circuit 12 is switched as shown by the solid line or the dotted line, and the output column address signal Ca is output to the output terminal 5 to the memory (not shown) and the last column detection circuit 13. Similarly, the output row address signal Ja is output to the output terminal 6 to the memory (not shown) and the last row detection circuit 14.

Each output of the last column detection circuit 13 and the last row detection circuit 14 is connected to a carry switching circuit 11, and is switched as shown by a solid line or a dotted line, and the output is sent to the carry terminal CI of the upper address counter 7 and the lower It is connected to the reset terminal R of the address counter 8.

The input terminal 1 of the reading start signal WS is connected to the set terminal S of the switching circuit 9 of the E-mode, the input terminal 2 of the reading start signal rs is connected to the reset terminal R, and the output terminal Q is connected to the clock signal WS. It is connected to the switching circuit 10, the carry switching circuit 11, and the address switching circuit 12, and when the write start signal WS is input to the mode switching circuit 9, the clock switching circuit 10. When the carry switching circuit 11 and the address switching circuit 12 are switched to the solid line side, and when the read start signal rs is input to the mode switching circuit 9, the clock switching circuit 10
The one-carry switching circuit 11 and the address switching circuit 12 are each switched to the dotted line side.

Next, the operation of the embodiment shown in FIG. 1 will be explained in detail with reference to FIG. 2. Here, the complete block has a configuration of (M bits in rows) x (N bits in columns) as shown in FIG. 2 (^). Further, the number of counter stages of the upper address counter 7 and the lower address counter 8 is set to the larger value of M and N.

When the write start signal WS is input to the input terminal 1, the output terminal Q of the mode switching circuit 9 becomes "1", and the clock switching circuit 109, carry switching circuit 11, and address switching circuit 12 move to the solid line side in FIG. I cut it. The lower address counter 8 counts up in response to the write clock WC input from the input terminal 3, and the output thereof is output by the address switching circuit 12 to the output terminal 6 and @row detection circuit 14 as the row address signal 1a. Ru. When the final row detection circuit 14 detects the final row M, its output is inputted to the carry terminal CI of the upper address counter 7 by the carry switching circuit 11, and the counter is incremented by +1, and the output is inputted to the carry terminal CI of the upper address counter 7. is input to the reset terminal R and is reset. The output of the upper address counter 7 is outputted by the address switching circuit 12 to the output terminal 5 and the final column detection circuit 13 as a column address signal Ca.

In this way, the column address signal Ca from O to N is output from the output terminal 5, and the row address signal 1a from O to M is output from the output @i terminal 6.

Next, when the read start signal rs is input to the input terminal 2, the output terminal Q of the mode switching circuit 9 becomes "0", and the clock switching circuit 101, carry switching circuit 11, and address switching circuit 121, as shown in FIG. Switch to the dotted line side.

The lower address counter 8 counts up in response to the read clock rc inputted from the input terminal 4, and its output is outputted by the address switching circuit 12 to the output terminal 5 and the final column detection circuit 13 as a column address signal Ca.

When the final column detection circuit 13 detects the final column N, its output is transferred to the upper address counter 7 by the carry switching circuit 11.
The counter is incremented by +1, and the lower address counter 8 is input to the reset terminal R and reset. The output t of the upper address counter 7 is outputted by the address switching circuit 12 to the output terminal 6 and the final row detection circuit 14 as a row address signal 1a.

In this way, the column address signal @Ca from 0 to N is output from the output terminal 5, and the row address signal 1a from O to M is output from the output terminal 6.

Note that (B) in FIG. 2 illustrates the state transition of an address in order to supplement the above explanation.

〔Effect of the invention〕

As explained above, the present invention reduces the circuit scale of the interleaving circuit by switching the output of the address counter with the mode (write/read) signal, so that the write address counter and the read address counter can be shared. There is an effect that can be done.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention, and FIG.
The figure is an explanatory diagram for explaining the same as above. 7... Upper address counter, 8... Lower address counter, 9... Mode switching circuit, 10... Clock switching circuit, 11... Carry switching circuit, 12... Address switching circuit, 13 . . . Last column detection circuit, 14 . . . Last row detection circuit. (A) Figure 2

Claims (1)

[Scope of Claims] A memory; a counter for an upper address and a counter for a lower address that generate address signals for the memory; A memory type interleaving circuit comprising: an address switching circuit that switches to a column address signal; and a mode switching circuit that controls the address switching circuit in a write mode or a read mode.