JPS6142305B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a Hamming code generation and check circuit for a storage device.

Conventionally, in a storage device that uses a 1-bit error correction-2-bit error detection code (Hamming code) as an error detection code for the storage contents of a storage element, the error detection code is added in units of M×N bytes of data. , a Hamming code generation circuit and a Hamming check circuit for performing the error correction and detection are required for M×N bytes. Therefore,
The error detection circuit occupies a large amount of hardware in the storage device, resulting in an increase in the cost of the device and a decrease in reliability.

An object of the present invention is to solve the above-mentioned conventional drawbacks by using a Hamming code generation circuit and a Hamming code correction circuit in a time-division manner, respectively, and to provide a low-cost and highly reliable Hamming code generation and check circuit for a storage device. There is a particular thing.

The circuit of the present invention uses an error correction detection code for correcting 1-bit errors in memory contents and detecting 2-bit errors for each M×N byte (M≧1 integer; N≧2 integer) of input data. In the Hamming code generation and check circuit for a storage device for the input data read from the storage device storing the input data to which a first predetermined exclusion is added for each M byte of the input data A first code generation circuit that repeatedly performs a sum calculation N times to generate a code for error correction detection code generation, and an intermediate generation result from this first code generation circuit and an intermediate generation previously given from its own circuit. a second code generation circuit that performs a second predetermined exclusive OR operation on the result; and intermediate generation results from the first code generation circuit and intermediate generation from the second code generation circuit. from the first code generation circuit and the second code generation circuit after the results are stored and the first code generation circuit and the second code generation circuit repeat the exclusive OR operation N times. A storage means for storing the obtained first error correction detection code signal; and a third predetermined exclusive OR operation is performed on the first error correction detection code signal from the storage means to obtain a second error correction detection code signal. a third code generation circuit that outputs an error correction detection code signal; and a first error correction detection code signal from the storage means and a second error correction detection code signal from the third code generation circuit. and a comparison circuit that compares the error correction detection code and the error correction detection code added in advance to the input data.

Next, the present invention will be explained in detail with reference to the drawings.

In this embodiment, addition modulo 2 and ordinary multiplication are used for calculations, and each Hamming bit is the even parity of the corresponding data. However, it is also possible to make odd parity the humming bit.

FIG. 1 shows the Hamming code generation matrix H and its submatrix _HD . In Hamming code generation, if Hamming bits P ₀ , P ₁ , P ₂ , P ₃ , P ₄ , P ₅ and P ₆ are represented by a vector P, then the vector P is expressed by the equation (1), as is well known. It is determined by 2) and (3).

P′=D・tH _D (1) P ₀ =P′ ₀ +P ₁ +P ₂ +P ₃ +P ₄ +P ₅ +P ₆ (2) P ₁ =P′ ₁ ,P ₂ =P′ ₂ ,…,P ₆ = P ₆ ′ (3) However, the reference symbol D is input data, and the reference symbol tH _D is a transposed matrix of the submatrix _HD . The humming check is performed by comparing the vector P obtained by equations (1), (2), and (3) with the humming bit R read out from the storage element. If the comparison result shows that they match, it is normal. If they do not match, it is detected as a 1-bit error and correctable (in the case of P ₀ ≠ R ₀ ) or a 2-bit error (in the case of P ₀ =R ₀ ).

FIG. 2 is a diagram showing a Hamming code generation circuit and its control circuit according to this embodiment. write data
100 (4 bytes) is selected by the selection circuit 10 and becomes data bits D0, D1, D2, D3, D4, D.
5, D6 and D7, and exclusive OR (addition modulo 2) circuits 20, 21, 22, 23, 24, 25,
26 and 27 to the D input of the Hamming register 30. The E input of the same register 30 is used to specify input data validity, and the input is logic '1'.
When , new data applied via the D input when the clock is input becomes the register contents, and when the logic is "0", the original register contents are held. The C input of the Hamming register 30 is an initial setting designation, and when the input is logic "1", all bits are initialized to logic "0" when a clock is input.
Outputs P0', P1, P of Hamming register 30
2, P3, P4, P5 and P6 are applied to exclusive OR circuits 21, 22, 23, 24, 25, 26 and 27 to generate intermediate Hamming bits, and also applied to exclusive OR circuit 31 to generate Hamming bits. Bit P0 is generated, humming bit 300
(P0, P1, P2, P3, P4, P5 and P
6) is output. The control circuit 40 controls the operations of the above circuits. A byte designation signal 400 is applied to the selection circuit 10 to perform byte selection control, and input data valid designation signals 410, 411, 412 and 413 are applied to the E input of each bit of the Hamming register 30 as shown in FIG. , the initial setting designation signal 420 is applied to the C input of the Hamming register 30, and performs the control described above.

FIG. 3 shows a time chart for explaining the operation of the Hamming code generating circuit shown in FIG. 2. The circuit operation order of the present invention will be explained below.

(1) All bits of the contents of the Hamming register 30 are initialized by the initial setting designation signal 420.

(2) Set byte designation signal 400 to byte 0 designation,
Data 1 of byte 0 selected by selection circuit 10
10 is an exclusive OR circuit 20, 21, 22, 2
3, 24, 25, 26 and 27 to the intermediate humming bits P'0, P2, P3, P4, P5
and P6 are generated and stored in the Hamming register 30. Since the intermediate Hamming bit P1 is unrelated to the data of byte 0 as shown in FIG. 1, the input data valid designation signal 410 is "0" and the contents of the Hamming register 30 remain unchanged.

(3) In the same way as in (2), byte 1 and byte 2
Hamming bits are generated for each byte and byte 3. However, when generating the intermediate Hamming bit, the output of the Hamming register 30
P'0, P1, P2, P3, P4, P5 and P
6 is also referenced, so when operating on byte 1, new intermediate Hamming bits are generated including the intermediate Hamming bit for byte 0. That is, when the operation for byte 3 is completed, the Hamming generation result (P' in equation (1)) for 4 bytes of data is obtained.

(4) The exclusive OR circuit 31 performs the processing of equation (2) and outputs the desired Hamming bit (P) 300.

FIG. 4 is a diagram showing the humming check circuit of this embodiment.

This Hamming check circuit checks Hamming bits P0, P1, P2, P3, P4, P5, and P6 generated by the Hamming code generation circuit 50 of FIG. 2 for data 100 read from a memory (not shown). Hamming bits R0, R1, R read out from the memory corresponding to the read data;
2, R3, R4, R5 and R6 as input signals, and bit-wise, that is, Hamming bits R0 and P0, R1 and P1, R2 and P2, R3 and P3, R4 and P4, R5 and P5, R6 and P6. A comparison circuit 60 that compares as follows, and this comparison circuit 60
Comparison results of bit correspondence S0, S1, S2, S
3, S4, S5, and S6.

The logical sum result from the logical sum circuit 70 is used as syndrome information 700, and when the syndrome information 700 is logic "1" and the comparison result S0=logic "1", it indicates a 1-bit error and a correctable fault. A logic "0" indicates a 2-bit error failure.

In addition, in the Hamming code check circuit of this embodiment, when the Hamming check result is found, all 4 bytes of the read data have been sent to the memory, so if the read data has a 1-bit error, the data is read out from the memory again. After correcting the errors, it is necessary to send this data out of the memory. This may lead to a decrease in processing speed, but in this case, a configuration may be adopted in which a Hamming code generation circuit for one byte of data is used and a Hamming code check circuit for four bytes is used.

Alternatively, a configuration may be adopted in which a Hamming code check circuit for one byte of data and a Hamming code generation circuit for four bytes of data are used.

The present invention has the advantage that a Hamming code generation and check circuit can be realized with a small amount of metal materials, and a highly reliable storage device can be provided at low cost.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a Hamming generation matrix used in one embodiment of the present invention, FIG. 2 is a diagram showing a Hamming generation circuit in one embodiment of the present invention, and FIG. 3 is a diagram explaining the operation of the present invention. FIG. 4 is a time chart showing a humming check circuit according to an embodiment of the present invention. In FIG. 1, FIG. 2, FIG. 3, and FIG. 4, 10... selection circuit, 20, 21, 22, 23, 2
4, 25, 26, 27, 31... exclusive OR circuit, 30... Hamming register, 40... control circuit.

Claims (1)

[Claims] 1 M×N bytes of input data (an integer of M≧1;
(an integer of N≧2) the input data read from the storage device storing the input data to which an error correction detection code for correcting 1-bit errors and detecting 2-bit errors in the stored contents is added in advance for each unit (integer of N≧2); In a Hamming code generation and check circuit for an input data storage device, a first predetermined exclusive OR operation is repeatedly performed N times for each M byte of the input data to generate an error correction detection code generation code. a first code generation circuit; and a second code generation circuit that performs a second predetermined exclusive OR operation on the intermediate generation result from the first code generation circuit and the intermediate generation result previously given from its own circuit. a second code generation circuit, which stores intermediate generation results from the first code generation circuit and intermediate generation results from the second code generation circuit; a storage means for storing a first error correction detection code signal obtained from the first code generation circuit and the second code generation circuit after a circuit repeats the exclusive OR operation N times; a third code generation circuit that performs a third predetermined exclusive OR operation on the first error correction detection code signal from the storage means and outputs it as a second error correction detection code signal; an error correction detection code consisting of a first error correction detection code signal from the means and a second error correction detection code signal from the third code generation circuit; and an error correction detection code added in advance to the input data. 1. A humming generation and check circuit for a storage device, characterized in that it is comprised of a comparison circuit for comparing .