JPS6334491B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION TECHNICAL FIELD The present invention relates to an error correction device that performs error correction used in an information processing device.

Prior Art Conventionally, in this type of error correction apparatus, received data and check bits are decoded, and if there is no error, the input data is output, and if there is an error, the error is corrected and output. Since this output data is operated so that it is valid both when there is no error and when there is an error, there is a drawback that the repetition cycle of the operation becomes long.

Furthermore, conventionally, if there is an error in the received data, an error correction circuit is activated by an error detection signal to correct it, which has the disadvantage that error correction becomes slow.

Purpose of the Invention An object of the present invention is to perform error correction in a cycle shorter than the operating cycle of the error correction means, and when it is necessary to perform error correction, switch to the error correction mode without waiting for the error detection result to shorten the operating cycle. To provide an error correction device which performs error correction by shortening the length, outputs data before error correction and data after error correction at different times, holds the data in a holding circuit, and supplies data with a long effective output time. There is a particular thing.

Structure of the Invention The error correction device of the present invention continuously receives data of a predetermined number of bits and error correction check bits corresponding to this data, and outputs data equal to the data and the error correction check bits in a first step. In the second step, an error correction means for outputting the corrected data, a selection means for selecting the output of the error correction means, a holding means for holding the output of the selection means, and the error correction means are alternately operated. control means for delaying a selection signal input to the selection means to cause the holding means to hold the error-corrected data when the error correction means detects an error, and outputting an error correction response signal. .

Next, the present invention will be explained in detail with reference to the drawings. Referring to FIG. 1, one embodiment of the present invention includes data, an error correction check bit signal 10 corresponding to the data, and an UP side clock signal 1.
8, and UP side correction signal 22 as input signals.
an UP side error correction circuit 1 whose output signals are a side correction data signal 11 and an UP side error detection signal 13;
signal 10, LOW side clock signal 19, and
a LOW-side error correction circuit 2 that uses a LOW-side correction signal 23 as an input signal and uses a LOW-side correction data signal 12 and a LOW-side error detection signal 14 as output signals;
The UP side correction data signal 11 and the LOW side correction data signal 12 are used as input signals, and the selection data signal 1
6 as an output signal, an error switching control circuit 5 that uses the UP side error detection signal 13 and the LOW side error detection signal 14 as input signals and outputs the data switching signal 15, and the selected data signal 16. and a data holding circuit 4 which uses the holding clock 20 as an input signal and uses the held data signal 17 as an output signal.

Here, Fig. 1 and time chart Fig. 2 a,
The operation of this embodiment in cases where there is no error in the data and cases where there is an error in the data will be explained in detail using .b.

Data signal 10 is data A at time 1, data B at time 2, data C at time 3, and data D at time 4.
If the UP side error correction circuit receives
Data A is input at time 1 and data C is input at time 3 by the UP side clock 18 input at the times shown in Figures a and b.
is taken in. Similarly, since the UP side correction signal 22 input to the circuit 1 is in the non-correction mode N at times 1 and 3 and in the correction mode T at times 2 and 4, the circuit 1 performs data error correction at times 2 and 4. The UP side corrected data signal 11 becomes the captured data A and C at times 1 and 3, and becomes the corrected data A' of data A and the corrected data C' of data C at times 2 and 4. On the other hand, the LOW side error correction circuit 2 uses the same signal 1 on the UP side.
When 0 is input, the LOW side clock 19 takes in data B at time 2 and data D at time 4. Similarly, the LOW side correction signal 23 input to the circuit 2 is in the uncorrected mode N at times 2 and 4, and in the correction mode T at times 3 and 5, so the circuit 2 performs error correction at times 3 and 5, and goes LOW. The side correction data signal 12 is the captured data B at times 2 and 4,
C and corrected data of data B at times 3 and 5.
B' becomes the corrected data D' of data D. If the selection circuit 3 determines that there is no error in the data, the selection circuit 3 is switched by the selection signal 15 from the error switching control circuit as shown in FIG. The data is taken into the holding circuit 4 and held data 17 is output.

If there is an error in the data C, the error detection signal 13 is output from the UP side error correction circuit 1, and upon receiving it, the error switching control circuit 5 causes the selection circuit 3 to select the UP side correction data 11 at time 4. The data switching signal 15 is outputted to. As a result, a selection data signal 16 is output, which is taken into the holding circuit 4 by the holding clock 20 and held data 17 is stored in the second
The output is as shown in Figure b.

In this manner, in this embodiment, data processing can be performed at one time interval even though the operation cycle of the error correction circuit is at two time intervals. Also, if the error correction circuit corrects the error after it is discovered, taking data C' as an example, it may not be possible to output data C' at time 4 in time, resulting in a longer operating cycle.This drawback should be removed. be able to.

Also, the data before error correction, the data after error correction are
The output is divided into two periods and held in a holding circuit to lengthen the effective output time.

In addition, in the above, UP side error correction circuit 1 and LOW
The UP side clock 18 and the LOW side clock 19 are input to the side error correction circuit 2, respectively.
Although the explanation has been made assuming that uncorrected data and, if there is an error, corrected data are output after a certain period of time, in reality, signals synchronized with clocks 18 and 19 are supplied to error correction circuits 1 and 2. The uncorrected data may be output at the first time, and the corrected data may be output at the second time.

Effects of the Invention The present invention includes two error correction circuits that output data equal to the input in the first stage and output corrected data in the second stage, and By configuring an error correction device that has a selection circuit that selects the output data of two error correction circuits and a holding circuit that holds the output of the selection circuit, error correction can be performed at a cycle shorter than the operating cycle of the error correction circuit. If it is necessary to perform error correction, switch to error correction mode without waiting for the error detection result, shorten the operating cycle, perform error correction, and perform error correction at different times for data before error correction and data after error correction. This has the advantage that it is possible to output data, hold it in a holding circuit, and supply data with a long effective output time.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an embodiment of the present invention, and FIGS. 2a and 2b are time charts for explaining the operation of the present invention. 1 and 2, 1...UP side error correction circuit, 2...LOW side error correction circuit, 3...
...Data selection circuit, 4...Data holding circuit, 5...
...Error switching control circuit, 6...Gate circuit, 10...
...data and error correction check bits corresponding to the data, 11...UP side correction data, 12
...LOW side correction data, 13...UP side error detection signal, 14...LOW side error detection signal, 15...
Data switching signal, 16... Selected data signal, 17
...Retained data, 18...UP side clock, 19
...LOW side clock, 20...Holding clock,
21... Correction signal, 22... UP side correction signal, 2
3...LOW side correction signal, A, B, C, D...data, A', B', C', D'...correction data for each of A, B, C, D, N...no correction mode , T...Correction mode.

Claims (1)

[Scope of Claims] 1. In an error correction device that continuously receives a predetermined number of bits of data and error correction check bits corresponding to the data and performs error correction, the data and the error correction check bits are received. a plurality of error correction means for outputting data equal to these data and error correction check bits in a first period and outputting corrected data in a second period; distribution means for sequentially loading the check bits into the plurality of error correction means; selection means for sequentially selecting the outputs of the plurality of error correction means; output holding means for holding the outputs of the selection means; and the plurality of error correction means. Until any of the error detection means detects an error, data in the first period of each error detection means is selected, and when any of the error detection means detects an error, the data of the first period of the error detection means that detected this error is selected. and control means for controlling the selection means to select data in two periods.