JPH06196920A - Phased array antenna system and its control circuit - Google Patents

Abstract

PURPOSE:To miniaturize the whole size of a device without requiring a specific terminal pin and to easily execute operation check by detecting an encoded reset signal included in a trigger signal. CONSTITUTION:A control circuit 1 for a phased array antenna system is provided with a reset signal detecting circuit 6 for detecting an encoded reset signal inserted into a trigger signal. When the encoded reset signal is applied together with the trigger signal T and detected by the circuit 6, a reset signal R is outputted to reset a coordinate detecting circuit 2, a data detecting circuit 3, a mode setting circuit 4, and a register 5. Namely the circuit 1 can share a terminal pin for the reset signal with a terminal pin for the trigger signal, so that the number of terminal pins can be reduced. Conse-qently operation check can simply be executed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phased array antenna device for controlling an active module in a phased array antenna device and a control circuit therefor.

[0002]

2. Description of the Related Art FIG. 7 is a block diagram showing a control circuit of a conventional phased array antenna device.
Reference numeral 1 denotes a control circuit (not shown), which is provided with a large number of control circuits 1 for each of the active modules provided for each of the plurality of antenna elements arranged on the X and Y coordinates. X, Y, D, T, R, and CK are various signals sent from a CPU (not shown) to each control circuit 1, and X and Y are X for selecting individual active modules. , A selection signal indicating the Y coordinate, D is data for controlling operation modes such as transmission, reception, and phase setting, T is a trigger signal for controlling operation timing controlled by the data D, and R is described later in the control circuit 1. A reset signal for resetting each circuit and CK are clocks for driving each circuit.

In the control circuit 1, 2 is a selection signal X, Y.
A coordinate detection circuit 3 for detecting the coordinates of the active module to be controlled by itself, a data detection circuit 3 for receiving the data D when the coordinate detection circuit 2 detects the coordinates, and a data detection circuit 4 for converting the serial data into parallel data. Is a mode setting circuit for setting an operation mode according to the content of the data D detected by the data detection circuit 3 based on the detection of the coordinate detection circuit 2, 5 is the coordinate detection circuit 2, the data detection circuit 3,
It is a control register that creates a control signal for controlling the active module to be controlled based on each output of the mode setting circuit 4 and the trigger signal T and supplies the control signal to the active module.

Each of the circuits 2, 3, 4, and 5 described above has a clock C.
It operates in synchronization with K and is reset by a reset signal R. The active module is composed of a transmission / reception circuit, an amplifier, a phase shifter, and the like.

Next, the operation will be described. The coordinate detection circuit 2 detects that the selection signals X and Y sent from the CPU coincide with the own coordinates. In response to this detection, the data detection circuit 3 reads the data D at that time, converts it into parallel data, and adds it to the mode setting circuit 4. The mode setting circuit 4 sends to the register 5 a signal for setting the operation mode according to the content of the data D. The register 5 sends a control signal to the active module to be controlled at the timing of the trigger signal T, and the active module operates in a mode according to the control signal to perform transmission, reception, phase control and the like. In addition, as shown in FIG. 8 from the CPU, the clock CK
When the reset signal R is sent in synchronism with, all the control circuits 1 are reset. The trigger signal T'changes according to the operation mode. In addition to the above-mentioned conventional technique, as a prior art, for example, Japanese Patent Laid-Open No. 63-48903
JP-A-62-121818.

[0006]

Since the control circuit of the conventional phased array antenna apparatus is configured as described above, the dedicated reset signal R is used to reset all the control circuits 1. Therefore, the control circuit 1 is provided with a terminal pin dedicated to the input of the reset signal R. However, when using several thousand antenna elements like a recent phased array antenna device, there is a problem that increasing the number of terminal pins hinders miniaturization.

Further, the operation of the active module is complicated and is usually controlled by several kinds of control signals. Therefore, when checking the operation of each active module, there is a problem that a large-scale measuring device for supplying several kinds of control signals to perform measurement is required.

The present invention has been made to solve the above-mentioned problems, and provides a phased array antenna device and a control circuit therefor which can reduce the number of terminal pins and can easily perform an operation check. The purpose is to get.

[0009]

A control circuit of a phased array antenna apparatus according to the invention of claim 1 is provided with a reset signal detection circuit for detecting a reset signal coded and inserted in a trigger signal. is there.

The control circuit of the phased array antenna apparatus according to the invention of claim 2 is an S / P conversion circuit for converting a reset signal coded and inserted in a trigger signal into parallel data, and a code for the parallel data. And a multi-input AND circuit having an inverting input terminal according to the above.

The control circuit of the phased array antenna apparatus according to the invention of claim 3 is provided with an operation mode detection circuit for detecting the operation mode code coded and inserted in the trigger signal.

According to a fourth aspect of the invention, the phased array antenna device is provided with a reset signal encoded in the trigger signal.

[0013]

In the control circuit of the phased array antenna device according to the first aspect of the present invention, the terminal pin for the reset signal can be shared with the terminal pin for the trigger signal, and the number of terminal pins can be reduced.

In the control circuit of the phased array antenna apparatus according to the invention of claim 2, since each bit of the parallel data of the coded reset signal is added to the multi-input AND circuit as it is or inverted, it is added to the positive or negative. A reset signal is obtained.

In the control circuit of the phased array antenna device according to the third aspect of the present invention, a plurality of types of control signals can be independently input to each control circuit from the terminal pin of the trigger signal without using a selection signal, and the operation check is easy. Can be done.

In the phased array antenna apparatus according to the invention of claim 4, since the reset signal can be given to all the control circuits by using the terminal pins of the trigger signal, the number of terminal pins of the control circuit can be reduced, The entire device can be downsized.

[0017]

EXAMPLES Example 1. An embodiment of the invention of claims 1 and 4 will be described below with reference to the drawings. In FIG. 1, parts that are substantially the same as those in FIG. In FIG. 1, reference numeral 6 denotes a reset signal detection circuit that detects the coded reset signal RD included in the trigger signal T and outputs the reset signal R. In FIG. 2, RD is a coded reset signal inserted in the trigger signal T.

Next, the operation will be described. A coded reset signal RD as shown in FIG. 2 is added together with the trigger signal T, and when the reset signal detection circuit 6 detects this, the reset signal R is output and the coordinate detection circuit 2,
The data detection circuit 3, the mode setting circuit 4, and the register 5 are reset.

Example 2. FIG. 3 shows an embodiment of the invention of claim 2 and shows an embodiment of the reset signal detection circuit 6. In FIG. 3, 7 is an S / P conversion circuit for converting serial data in the trigger signal T into parallel data, 8 is a multi-input AND circuit to which parallel data obtained from the S / P conversion circuit 7 is added, In this embodiment, a multi-input NAND gate having an inverting input terminal corresponding to parallel data is used.

FIG. 4 shows an example of the coded reset signal RD. In this example, the reset signal RD is "01101" during the timing of the reception mode of the trigger signal T.
It is coded as serial data having a 6-bit binary code "0". In response to this, the first, fourth, and sixth bits of the multi-input terminal of the multi-input NAND gate 8 are inverting input terminals.

Next, the operation will be described. The S / P conversion circuit 7 has a coded reset signal R as shown in FIG.
When D is added, the serial data becomes “01101
It is converted into parallel data of "0". By applying this data to the multi-input NAND gate 8, the reset signal R as a negative pulse is obtained from the multi-input NAND gate 8.

Example 3. FIG. 5 shows an embodiment of the invention of claim 3, and the same parts as those in FIG. In FIG. 5, reference numeral 9 denotes an operation mode detection circuit 9 for detecting operation mode data SD indicating the operation mode included in the trigger signal T, and the detected operation mode is added to the mode setting circuit 4.

In FIG. 6, SD is the operation mode data, which is inserted in a different position together with the reset signal RD coded in the trigger signal T.

Next, the operation will be described. When checking the operation of the active module, the operation mode data SD is inserted into the trigger signal T and added to the control circuit 1.
This operation mode data SD is different from the operation mode included in the data D and without using the selection signals X and Y.
It is entered independently. This is detected by the operation mode detection circuit 9, and a signal indicating the operation mode is applied to the mode setting circuit 4. The mode setting circuit 4 controls the active module with a control signal indicating the operation mode.

[0025]

As described above, according to the first aspect of the present invention, since the coded reset signal included in the trigger signal is detected, the terminal pin for the reset signal can be omitted. As a result, there is an effect that the terminal pin for the reset signal of the control circuit of the entire phased array antenna device is eliminated and the entire device can be downsized.

According to the second aspect of the present invention, the coded reset signal included in the trigger signal is converted into parallel data and then added to a multi-input AND circuit having an inverting input terminal according to the code. Therefore, there is an effect that the reset signal can be reliably detected with a simple circuit.

According to the invention of claim 3, since the operation mode code included in the trigger signal is detected, a plurality of kinds of control signals for checking the operation of the active module are used as the selection signal or the like. There is an effect that it can be added independently and the operation check can be performed easily.

According to the invention of claim 4, the coded reset signal is provided in the trigger signal.
There is an effect that terminal pins for reset signals of all control circuits can be eliminated, and the phased array antenna device can be downsized.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the invention of claim 1;

FIG. 2 is a timing chart showing the operation.

FIG. 3 is a circuit configuration diagram showing an embodiment of the invention of claim 2;

FIG. 4 is a timing chart showing an operation.

FIG. 5 is a block diagram showing an embodiment of the invention of claim 3;

FIG. 6 is a timing chart showing an operation.

FIG. 7 is a block diagram showing a control circuit of a conventional phased array antenna device.

FIG. 8 is a timing chart showing an operation.

[Explanation of symbols]

 1 control circuit 6 reset signal detection circuit 7 S / P conversion circuit 8 multi-input NAND gate (multi-input AND circuit) 9 operation mode detection circuit X, Y selection signal D data T trigger signal R reset signal RD coded reset signal SD operation mode data

Claims (4)

[Claims] 1. A control circuit provided for each active module connected to each of a plurality of antenna elements and performing operations such as transmission, reception, and phase setting, which is input when selected by a selection signal. The phased signal is configured to take in data indicating an operating mode, etc., generate a control signal for controlling the corresponding active module based on this data and the input trigger signal, and to be reset by the reset signal. A control circuit for an array antenna device, comprising a reset signal detection circuit for detecting a coded reset signal included in the trigger signal. 2. A control circuit connected to each of a plurality of antenna elements and provided for each active module that performs operations such as transmission, reception, and phase setting, which are input when selected by a selection signal. It is configured to take in the data indicating the operating mode etc., generate a control signal for controlling the corresponding active module based on this data and the input trigger signal, and to reset by the input reset signal. In the control circuit of the phased array antenna apparatus, the S / P conversion circuit for converting the coded reset signal included in the trigger signal into parallel data and the parallel data obtained from the S / P conversion circuit are added. Providing a multi-input AND circuit having an inverting input terminal at a position corresponding to the parallel data A control circuit for a phased array antenna device, characterized in that. 3. A control circuit provided for each active module connected to each of a plurality of antenna elements and performing operations such as transmission, reception, and phase setting, which is input when selected by a selection signal. In the control circuit of the phased array antenna device, which is configured to take in data indicating the operating mode, etc., and generate a control signal for controlling the corresponding active module based on the data and the input trigger signal, the trigger signal 2. A control circuit for a phased array antenna device, comprising: an operation mode detection circuit for detecting the operation mode data indicating the operation mode included in, and outputting a signal for producing the control signal. 4. A control circuit connected to each of a plurality of antenna elements and provided for each active module for performing operations such as transmission, reception, and phase setting, which is input when selected by a selection signal. The control is performed so as to take in the data indicating the operating mode etc., generate the control signal for controlling the corresponding active module based on the data and the input trigger signal, and reset the reset signal by the reset signal. A phased array antenna device having a circuit, wherein a reset signal coded in the trigger signal is provided.