JPH0823764B2 - Multi-channel analog output circuit - Google Patents

Description

The present invention relates to a multi-channel analog output circuit of a programmable control system, and is particularly suitable for a programmable control system requiring low noise resistance at low cost. Multi-channel analog output circuit.

[Conventional technology]

In a programmable control system (hereinafter referred to as PCS) that automatically controls a plurality of devices based on preset programs and predetermined input data using a computer,
A multi-channel analog output circuit is required as an interface between the output and the controlled device.

The function required for this PCS is to hold digital data of multiple channels that are periodically updated, and to electrically isolate the analog data of multiple channels corresponding to the digital data of these multiple channels, respectively. Therefore, in the conventional apparatus, as shown by 10 in FIG. 2, the flip-flops 7a to 7d for storing digital data for each of a plurality of output channels and the analog signals for the flip-flops 7a to 7d are stored. D / A (digital-to-analog) converters 1a to 1d for converting into quantities, and operational amplifiers 8a to 8d which are buffers of analog quantity are provided, and by the channel selection signal generated by the decoder circuit 5,
The output data from the PCS main unit was stored in the flip-flops 7a to 7d, converted into an analog amount, and output.

Further, at this time, considering the induction from the controlled device connected to the external wiring side and the wiring for it, in order to enhance the noise resistance, the photo coupler 3a, 3b is provided, electrically between the input and the output. It is designed to be isolated. This example shows the case where each channel is composed of 8-bit digital data input and the number of channels is 4 channels. Therefore, 9 is a 4-channel buffer circuit.

From the PCS main unit, the digital data DATA of each channel from No. 1 to No. 4 consisting of 8 bits are sequentially input in a predetermined cycle in a time-sharing manner, and the 2-bit address is input in parallel at the same time. It is distributed to each channel by the data ADDRES and supplied as each analog output of CH1 to CH4.

Examples of devices related to this type of device include, for example, "Countermeasures for analog circuit troubles" issued by CQ Publishing Co., Ltd., January 20, 1981, 4th edition, page 280, FIG.
I can give you 4.

[Problems to be solved by the invention]

The above-mentioned prior art does not consider the influence of noise on the buffer register on the digital side or the number of D / A converters used, and has a problem in terms of cost reduction of noise resistance. That is, in the above-mentioned prior art, as shown in FIG. 2, the buffer register for storing digital data is essentially composed of flip-flops 7a-7b which are weak against noise, and these are external signals of the photocoupler 3a. Since it is provided on the side (external wiring side of PCS), the digital data here is easily affected by noise.

Also, if the data on the flip-flops 7a-7b is changed due to noise in this way, the PC
Until the next data update time by S comes, analog data based on the incorrect data will continue to be output, and the influence of noise will appear significantly.

Furthermore, in this conventional technique, a D / A converter is required for each channel, and as a result, the conventional technique has problems in noise resistance and cost reduction.

An object of the present invention is that the effect of noise on the buffer register on the digital data side is small, and the effect of data change due to noise is small, and sufficient noise resistance can be obtained.
Another object of the present invention is to provide a multi-channel analog output circuit in which the number of expensive circuit elements is small and the cost can be easily reduced.

[Means for solving problems]

The purpose of the above is to provide a buffer register for holding digital data on the PCS side of an electrical isolation means such as a photocoupler, and to provide analog data holding means of the same number as the number of channels of data, and to provide each data from the buffer register. Digital data that is read cyclically for each channel is D / A converted and written sequentially to the analog data holding means corresponding to each channel, and the read cycle at this time should be shorter than the write cycle. It is achieved by

[Work]

The influence of noise on the buffer register that holds the digital data is electrically isolated, and the incorrect analog data is output by performing the read operation in a cycle shorter than the writing of the digital data to the buffer register. The noise resistance is improved because the period of occurrence of noise is shortened.

Further, since each channel can be sequentially read from the buffer register and D / A converted, only one D / A conversion means is required regardless of the number of channels, and cost reduction is easy.

〔Example〕

Hereinafter, the multi-channel analog output circuit according to the present invention will be described in detail with reference to the illustrated embodiments.

FIG. 1 shows an embodiment of the present invention, which is the same as the conventional example shown in FIG. 2 as a multi-channel analog output circuit of PCS for outputting 8-bit and 4-channel digital data as an analog signal to the external wiring side. In the figure, 1 is a D / A converter, 2a to 2b are S / H circuits (sample and hold circuits), 4 is a dual port RAM, 6 is a frequency dividing circuit, and others are This is as described with reference to FIG.

The dual port RAM4 has four 8-bit registers Reg.1 to Reg.4 set internally.
The g.1 to 4 are sequentially written and selected by the address ADDRESS supplied from the POS, and the data DATA of 4 channels are sequentially written cyclically for each channel.

The write cycle at this time is set to, for example, about 40 to 100 msec, but in this embodiment, it is set to 40 msec. Therefore, the data of each register Reg.1 to 4 is sequentially set every 10 msec. As a result, the data for each channel was changed to 40.
It will be updated in m seconds.

On the other hand, the frequency divider circuit 6 divides the clock CLK supplied from the PCS to output a 2-bit address a, and this address a causes the registers Reg. 1 to 4 of the dual port RAM 4 to be read and selected. The decoder circuit 5 outputs sample pulses Y _{0 to} Y ₃ by this address a and supplies them to the S / H circuits 2a to 2d of the respective channels via the photocoupler 3b. The cycle of the address a by the frequency dividing circuit 6 at this time is set to 1 msec.
This address a moves to the next every 0.25 ms, and returns to the original address in 1 ms.

Therefore, each register Reg.1 to 4 of dual port RAM4
Is the address a (Reg.ADDRES
S) are sequentially read out and selected by each register Reg. 1 to 4
The 8-bit data written in is sequentially read every time the address a changes, and is read out via the photo coupler 3a.
It is input to the A converter 1 and converted to analog, and the S / H circuits 2a to 2d
Will be supplied to.

By the way, the S / H circuits 2a to 2d are connected to the sample pallets Y ₀ to
It is controlled by Y ₃ , which results in these S / H circuits 2
Each of a to 2d stores the analog data appearing at the output of the D / A converter 1 each time the corresponding sample pallet Y _{0 to} Y ₃ is input, and then again the corresponding sample pulse. Until Y _{0 to} Y ₃ appear, it keeps outputting the previously stored analog data to the external wiring side.

And each register Reg.1 to 4 of dual port RAM4
Read select also, the sample pulse S / H circuits 2a-2b Y ₀ to Y ₃
Are also controlled by the address a, and as a result, the data read from the register Reg.1 of the dual port RAM4 is sampled and held in the S / H circuit 2a, and so on. / H circuit 2b, the data of register Reg.3 is S / H circuit 2c, and the data of register Reg.4 is
The S / H circuit 2d is to be stored and held respectively, and its cycle is 1 ms.

On the other hand, as described above, the data write cycle for each register Reg. 1 to 4 of the dual port RAM 4 is 40 msec, and these write cycle and read cycle are independent.

Therefore, according to this embodiment, the dual port RAM 4 functioning as a buffer register for digital data is electrically isolated from the external wiring side by the photocouplers 3a and 3b, and therefore, even on the external wiring side. Even if the noise environment is poor, there is almost no risk that the data in the dual port RAM4 will be affected.

According to this embodiment, the Kana log output data is S /
It is designed to be held by the H circuits 2a to 2b and is directly connected to the external wiring side, but since this S / H circuit holds data as analog signals, it is less susceptible to noise. Further, even if noise is mixed in, there is little possibility that a large data change will occur, and according to this embodiment, the sample and hold periods of these S / H circuits 2a to 2d are set to the registers Reg.1 of the dual port RAM4. ~ 4 data update cycle,
In other words, it is 1 ms, which is sufficiently shorter than that, regardless of the data update cycle by the PCS body, so even if S / H
Even if the analog data of the circuits 2a to 2d is changed by noise, it is corrected to a correct value within 1 msec at the maximum, so that the influence of noise is sufficiently suppressed.

Next, the operation of this embodiment will be described in more detail with reference to the timing chart of FIG.

In FIG. 3, (a) is an address a generated by the frequency dividing circuit 6, which cyclically generates the addresses of the channels CH1 to CH4.

In response to this address a, the decoding circuit 5 sends the sample pulses Y _{0 to} Y ₃ shown by the waveform (3) to the S / H circuit 2 to hold the analog amount.

Here, if the scanning timing of CH1 to CH4 by the address a is a self scan cycle, this self scan cycle is 1 msec, and the PCS shown by d in FIG. 3 (6).
The time is set to be sufficiently shorter than the scan time (40 ms) by the main body.

Therefore, the channel CH1 shown by the waveform c in FIG.
Focusing on the analog output waveform of, even if the analog output value changes temporarily due to external noise at the timing of (1), it is correct output at a timing (2) which is very short time after the self-scan cycle. It shows that the value is recovered.

If the same phenomenon occurs in the conventional circuit shown in FIG. 2, the correct value is restored until timing (3) in the waveform c of FIG. 3 (5), that is, at the maximum until the next scan time of the PCS body. Since the scan time of the PCS itself depends on the length of the user's program, there is no guarantee that it will stay at 40 ms as described above, and this recovery time may be further extended. On the other hand, according to the embodiment of the present invention, as described above, the analog output value is recovered to the correct value within 1 ms.

By the way, in the above embodiment, the scanning by the PCS main body and the scanning by the analog output circuit are not particularly synchronized. And because of this the PC
There is a possibility of so-called competition in which writing of data from the S main unit and reading of data from the analog output side occur simultaneously.

However, in the above embodiment, since the dual port RAM is used as the multi-channel buffer register and the bidirectional access between the PCS main body side and the analog output side is possible, the fear of conflict can be eliminated.

It is needless to say that, instead of this, the scan by the CPS body and the self scan on the analog output side may be performed in synchronization with each other so that no conflict occurs.

[Effect of the Invention] According to the present invention, the influence of noise from the external wiring side can be made to appear mainly only on analog data, and the time until its recovery can be made sufficiently short. It is possible to improve reliability and reliability.

Further, according to the present invention, only one D / A conversion means need be provided irrespective of the number of channels of data, and cost reduction is easy.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a multi-channel analog output circuit according to the present invention, FIG. 2 is a block diagram of a conventional example, and FIG. 3 is a time chart for explaining the operation. 1 …… D / A converter, 2a to 2d …… Sample and hold (S / H) circuit, 3a, 3b …… Photo coupler, 4 …… Dual port RAM, 5 …… Decoder circuit, 6 …… minute Circular circuit, 10 ... Multi-channel analog output circuit.

Claims (4)

[Claims] 1. Digital data of a plurality of channels, which are periodically updated, are held, and analog data of a plurality of channels corresponding to each of the digital data of the plurality of channels are electrically isolated and continuously independent. In the multi-channel analog output circuit for outputting the multi-channel analog output circuit, the multi-channel buffer register means for holding the digital data of the plurality of channels for each channel, and the digital data read for each channel from the multi-channel buffer register means. The digital / analog conversion means for electrically isolating the data into analog data and the multi-channel analog data holding means for independently holding the output of the digital / analog conversion means for each channel are provided. Digital for each channel of far register means Multi Channel analog output circuit, characterized in that set in the shorter period than the update period of the digital data to the multi-Channel punishment Hua register means reading period of the over data. 2. A multi-channel analog output circuit according to claim 1, wherein said multi-channel buffer register means comprises a dual port random access memory. 3. A multi-channel analog output circuit according to claim 1, wherein said multi-channel analog data holding means comprises a plurality of sample and hold circuits. 4. A multi-channel analog output circuit according to claim 1, wherein said means for electrically isolating comprises a photo coupler.