SU1545210A1 - Device for interfacing analog-digital converter and micrpoprocessor - Google Patents

Abstract

The invention relates to electronic technology and can be used to interface primary data converters, such as analog-digital, with a microprocessor. The purpose of the invention is to increase the device speed by automatically switching the interface device to its initial state immediately after reading the sign of the completion of the next cycle of the converter operation and the formation of a ready signal. The device contains two triggers, the And element, the buffer register, the address selector, the buffer amplifier. 2 Il.

Description

The invention relates to electronic engineering and can be used to interface primary data converters, such as an analog-to-digital converter (ADC), with a microprocessor.,

The aim of the invention is to improve the speed of the device by optimizing the process of asynchronous exchange and automatic transition of the interface device to the initial state immediately after reading the sign of the completion of the next cycle of the converter.

Figure 1 shows the functional electrical circuit of the device proposed; 2 shows timing diagrams for his work.

The device contains a converter of information, made in the form of analog-digital converter 1, first trigger 2, element 3, second trigger 4, buffer register 5, address selector 6, buffer amplifier 7 and microprocessor 6.

The information output of the converter 1 is connected to the information input of the buffer register 5, the output of which is connected to the common bus of the microprocessor 8, which also connects the output of the buffer amplifier 7 and the input of the selector 6, the output of which is connected to the control input of the buffer amplifier 7, the input resolution of the buffer, register 5 and synchronous trigger 4, output

which is connected to the information input of the buffer amplifier 7, the enable input of the recording of the buffer register 5, the second input of the AND 3 element and the R input of the trigger 2, the synchronous input of which is connected to the synchronization output of the converter 1, and the output connected to the first input of the And 3 element whose output is connected with the S-input of the trigger 4, on the D-input of the trigger 2 a logic level 1m is fed, to the D-input of the trigger 4 - the logic level O.

Converter 1 may be, for example, an analog-to-digital converter having an information output and a ready signal output, which is the second output of converter 1. As converter 1, for example, a KP13PV1 chip is used in an autonomous periodic start mode.

The buffer register 5 provides for fixing the output state of converter 1 at the end of each cycle of analog-digital conversion, as well as connecting it to the common microprocessor exchange bus 8. With the quality of buffer register 5 in the proposed device, a K588IR1 chip can be used, having control write inputs and reading, as well as in the absence of a reading signal, the third state of output tins (high impedance state),

Buffer amplifier 7 serves to connect the output of trigger 4 to the common bus of microprocessor 8 (if there is a read signal from the selectors of signals on the control input of amplifier 7) and can be performed, for example, on the basis of a K561LLN1 chip having the third output state (high impedance

The selector 6 serves to generate a read signal (when the microprocessor 8 accesses a predefined address corresponding to the primary information converter selected for reading), through which buffer register 5 and buffer amplifier 7 exit from the third state, supplying the corresponding information to the interface buses (data) which is then read by microprocessor 8 Practical - implementation of the selector 6

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From 1 to 5 of the type of microprocessor 8 and can be performed according to any of the known schemes, for example, for the microprocessor KI801BM2 can be made on the basis of the chips of the address decoder K588BTI and the element OR-NOT of the chip K561LE5. In this case, the OR-NOT element, if there are signals and LBT at its outputs from the corresponding outputs of the K5888BT1 chip, produces the output signal of the selector 6. Other variants of the technical implementation of the selector 6 for generating control signals are possible.

 The microprocessor 8 can have, for example, built-in or external operational storage and permanent storage memory (RAM and ROM) included in a typical scheme. The program memory of the microprocessor of the processor is stored in the ROM, and the RAM is a buffer for storing all intermediate results and operations.

25 The device operates as follows.

During the operation of the converter 1, signals at its synchronization output are periodically generated, indicating the end of the input information conversion process (Fig. 2, q), according to which trigger 2 (Fig. 2, 6) is activated.

The microprocessor 8 constantly reads the state of trigger 4 (by means of buffer amplifier 7) and buffer register 5. At the same time, the selector 6 periodically generates a reading signal, through which the buffer register 5 is connected to the common exchange bus of microprocessor 8 (FIG. 2, b).

Due to the fact that the microprocessor polling 8 causes the output state of trigger 4 and buffer register 5 to be unsynchronized with the moments of the end of operation of converter 1 (readiness of the converted information for transfer to microprocessor 8), there are several possible variants of operation of the device, which is shown schematically in Fig. 2.

If trigger 2 is cocked during the formation of a reading signal at the output of the selector 6, the latter, by means of the element And 3, locks

trigger 4, which eliminates the transfer of erroneous information to the microprocessor 8, which can

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occur due to transient processors associated with overwriting information from the first output of converter 1 to buffer register 5. Trigger 4 is reset immediately after the output signal of the read signal disappears at the output of selector 6, and the output information from converter 1 to the microprocessor 8 In this case, it is produced when the selector 6 develops the next reading signal. When trigger 4 is triggered, trigger 2 is reset immediately, and trigger 4 is reset upon completion of the read signal from the output of selector 6 (Fig. 2.3).

If trigger 2 is set between the read signals generated at the output of selector 6, then the output signal of trigger 2 directly inputs trigger 4, the output of which, in turn, resets trigger 2. Trigger 4 clears at the end of the next read signal from the output of the selector 6.

Claims (1)

Invention Formula A device for interfacing an analog-to-digital converter with a microprocessor, comprising an address selector, a buffer register, the information input of which is the input of the device for connection to the information analog-to-digital conversion Q 5 0 5 about five 106 the body and the FIBC input is the output of the device for connecting to the microprocessor data, the information input of the address selector is the input of the device for connecting to the microprocessor control bus, the output of the address selector is connected to the read enable input of the buffer register, which is designed to improve the speed of the device The element I, the first and second triggers and the buffer amplifier, the output of which is connected to the output of the device for connecting the microprocessor to the data bus, are entered into it. Gera is a device input for connecting an analog-to-digital converter to the ready output, the output of the first trigger is connected to the first input of an AND element, the output of which is connected to the setup input of the second trigger whose output is connected to the reset input of the first trigger, the enable input of the buffer register and the information input the buffer amplifier, the control input of which is connected to the output of the address selector, the second input of the element I and to the sync input of the second trigger, the information input of the first trigger n It is connected to the device's unit potential potential, and the information input of the second trigger is connected to the device potential zero bus. s, to // l Kwl 00 & %% FIG. 2