JPS638487B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION This invention relates to an interface device used for processing analog signals in a computer.

A conventional example of this type of interface device was constructed as shown in FIG. In Figure 1,
Reference numeral 1 denotes an analog signal input section into which analog signals A ₁ to A _o are input, and the analog signal input to this input section 1 is input to an analog multiplexer 2 . This multiplexer 2 is controlled by a control signal from the first bus interface section 5, selects a predetermined signal from the input analog signals, and inputs it to the sample hold section 3. A control signal is also input from the first bus interface section 5 to the sample hold section 3, and this control signal causes the analog/digital (hereinafter referred to as A/
An analog signal is input to the converter section 4 (referred to as D). The A/D converter section 4 is also given a control signal from the first bus interface section 5, and a digital signal is sent to the output of the converter section 4.
This digital signal is sent to the second bus interface section 6.
The information is input to, for example, a computer (not shown) via the computer. Note that the first bus interface unit 5 is connected to, for example, a computer (not shown).

Of the first and second bus interface sections 5 and 6 as described above, the first bus interface section 5 in particular obtains control signals to be applied to the multiplexer 2, sample and hold section 3, and A/D converter section 4. It is necessary to use a program such as a computer. For this reason, there is a drawback that the programs for computers and the like become complicated. Further, when controlling each of the above-mentioned sections 2 to 4 with a control signal, it is necessary to use a computer to manage the time for waiting until the analog signal in each section 2 to 4 settles down, so there is a drawback that the computer's programming method becomes sophisticated.
Further, although an interface device such as that shown in FIG. 1 is normally formed on a single printed board, it is difficult to test this device using only one printed board.

SUMMARY OF THE INVENTION An object of the present invention is to provide an interface device that eliminates the above-mentioned drawbacks, simplifies programming, and facilitates testing and adjustment.

An embodiment of the present invention will be described below with reference to the drawings, in which the same parts as in FIG. 1 are denoted by the same reference numerals.

In FIG. 2, reference numeral 11 denotes a first photocoupler section into which a control signal from a first interface section 5, the details of which will be described later, is input;
The control signals are electrically insulated and supplied to the analog multiplexer 2 and sample hold section 3, respectively. Note that the control signal supplied to the A/D converter section 4 is given from the first photocoupler section 11 via the waveform modification section 12. When the A/D converter unit 4 is supplied with the output of the waveform correction unit 12, it outputs a digital signal, but this signal is electrically isolated by the second photocoupler unit 13 and input to the second interface unit 6. be done. The digital signal input to the second interface section 6 is supplied to a computer (not shown) and processed. When the digital signal is sent out from the second interface section 6, the output display section 14, which is a light emitting diode, emits light to identify that the digital signal is being sent out. 15 is a flip-flop, and this flip-flop 15 has a first photocoupler section 1.
A start signal for the A/D converter section 4 sent from the converter section 1 and a control end signal output from the converter section 4 are supplied. flipflop 1
5 receives the control end signal and inputs its output to the first interface section 5 via the second photocoupler section 13. Note that the first interface section 5
The data latch signal DL, ready signal RY, and channel selection signal CH sent from the second interface section 6 are supplied to the second interface section 6.

Here, the specific configuration of the first interface circuit 5 will be described with reference to FIG. In Figure 3, 3
Reference numeral 1 denotes a read data input section, and upper and lower data UDR and LDR are input to this input section 31 from a computer or the like (not shown). The data supplied to the input section 31 is input to a control signal generation section 32 formed from a flip-flop, and the start signal ST of the A/D converter section 4 and the sample hold signal SH supplied to the sample and hold section 3 are outputted from the control signal generation section 32. Sent out. 33 is a clock signal generating section, and the output of this clock signal generating section 33 is supplied to the data input section 31. This clock signal is sent out by turning on switch 33a only during testing. Reference numeral 34 denotes an initialization signal and external reset signal input section, and the output of this input section 34 is supplied to the control signal generation section 32. 3
Reference numeral 5 denotes an end signal END input section that notifies that the signal processing of the A/D converter section 4 has ended, and the signal input to this input section 35 is input to the second photocoupler section 1.
Supplied from 3. The output of this termination signal input section 35 is supplied to the control signal generation section 32 and
is supplied to the second interface section 6 as a data latch signal DL. 36 is a channel update section, and this update section 36 is a DIP type switch 36a that can be set according to the number of analog signal input channels.
, a comparator 36b to which the output of this switch 36a is supplied, and a flip-flop 36c to which a sample and hold signal SH is input.
The output of the flip-flop 36c is the comparator 3.
6b, and its output is supplied to the switch 36a.
If it matches the value set in , the number of channels will be reset.

FIG. 4 is a detailed diagram of the second interface section 6, which is formed from a flip-flop.

Next, the operation of the above embodiment will be described. The analog signal input to the analog signal input section 1 is supplied to an analog multiplexer 2. Channel numbers CHo to CHn, which are control signals for the number of channels set by the channel update unit 36 of the first interface unit 5, are supplied to the multiplexer 2.
According to the channel numbers CHo to CHn, analog signals are inputted from the multiplexer 2 to the sample and hold section 3, and sequentially inputted to the A/D converter section 4 according to the sample and hold signals. A/
The first interface section 5 is also connected to the D converter section 4.
A start signal ST is supplied from the first photocoupler section 11 through the first photocoupler section 11, and a digital signal is obtained at its output. This digital signal is input to the second interface section 6 via the second photocoupler section 13.
The second interface unit 6 supplies the input digital signal to a computer or the like for signal processing.

As described above, since the control signal of the first interface section 5 is supplied to each section via the photocoupler, malfunctions due to noise and the like are extremely reduced.

As described above, according to the present invention, since a channel update section that can be changed according to the number of analog signal channels is provided in the first interface section, it is no longer necessary to create a change signal by a program, thereby simplifying the program. In addition, since the clock signal for testing can be supplied to the control signal generating section, there is an advantage that test adjustment can be easily performed by using this clock signal.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a conventional example, FIG. 2 is a block diagram showing an embodiment of the present invention, and FIGS. 3 and 4 are specific configuration diagrams of the main parts of FIG. 2. 5...first interface section, 6...second interface section, 11...first photocoupler section,
13...Second photocoupler section, 32...Control signal generation section, 33...Test clock signal generation section, 36
...Channel update department.

Claims (1)

[Claims] 1. An analog multiplexer to which an analog signal is input, a sample-and-hold circuit section to which the output of this multiplexer is supplied, and an analog-to-digital conversion to which the output of this circuit section is supplied and obtains a digital signal as an output. a first interface section to which program commands from a computer are supplied and which supply control signals to the multiplexer, sample-and-hold circuit section, and analog-to-digital converter section according to the commands; and a control signal from the first interface section. and a second interface section that inputs a digital signal controlled by the controller and output to the analog-to-digital converter section into a computer, wherein the first interface section receives upper and lower data as input. a clock signal generation section that supplies a clock signal to this data input section only during testing; and a clock signal generation section that receives data from the data input section and outputs the sample and hold circuit and an analog-to-digital conversion section. a control signal generating section that supplies a control signal to the sample and hold circuit; a control signal that is supplied from the control signal generating section to the sample and hold circuit; and an output controlled by the control signal and a preset number of analog signal input channels. An interface device comprising: a channel update unit that provides a channel number control signal to the analog multiplexer when a match occurs.