JP2883664B2 - Analog-to-digital converter - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an analog-to-digital converter, and more particularly, to an improvement in a data capturing method when an arbitrary number of analog-to-digital converters having the same configuration are operated in parallel. .

<Conventional technology> In a data storage device that uses an analog-to-digital converter (hereinafter, analog / digital is abbreviated as A / D) and converts and collects analog input signals of a plurality of channels into digital signals, a data storage device is used during a measurement There is a data storage device capable of sequentially storing all the data from the head address of the memory. This is a configuration in which data sampled immediately after the start of measurement can be stored at the head address of the memory. Particularly, when the A / D converter is operated using an external sample clock, it can be used as a digitizer that uses the external sample clock as a strobe pulse. That is, the input signal sampled at the timing of the strobe pulse that first enters after the start of the measurement can always be treated as the first measurement data.

The "A / D converter" of Japanese Patent Application No. 1-125238 filed by the applicant of the present application makes it possible to align the start timing of A / D conversion of each device and to control the trigger operation between the devices in association with each other. This is an A / D converter that can be driven in parallel. Seventh
The figure illustrates the principle. In the figure, 1a is the clock
A sample clock control circuit that controls the generation and switching of CLK, selectively outputs an internal reference clock, an externally applied external clock, and an external reference clock to an external unit as an external reference clock, and also outputs the internal reference clock to various internal units. Reference numeral 2 denotes an A / D converter which converts an analog input signal into a digital signal according to a clock CLK applied from the sample clock control circuit 1a. Reference numeral 3 denotes a data memory for storing output data of the A / D converter 2. 4a is a measurement enable signal AEN and a measurement start signal AS with an external device (not shown).
T is a data memory control circuit that transmits and receives a plurality of measurement control signals including a trigger enable signal TEN and controls the data storage operation of the data memory 3 in accordance with the measurement control signals. Reference numeral 5 denotes a trigger control circuit which selectively outputs an externally applied individual trigger signal and a synchronous trigger signal as a synchronous trigger signal to the outside, and stores a trigger signal TRIG synchronized with a clock supplied from the sample clock control circuit 1a in a data memory. Output to the control circuit 4a. Numeral 6 denotes an arithmetic control unit (CPU) which controls each unit, and is connected to each unit via a bus 7.

FIG. 8 is an explanatory diagram of a parallel connection state of the A / D converter configured as shown in FIG. 7, and shows an example in which K units are connected in parallel. In the figure, No. 1 functions as a master unit, and the other Nos. 2 to No. K function as slave units. Switching between the operation of the master unit and the operation of the slave unit is performed under the control of the trigger control circuit 5 in each unit. The individual trigger signal is applied only to the master device, and the analog input signal is applied to each device.

An external clock is commonly applied to all devices as needed. The output terminal of the external reference clock of the master unit, the output terminal of the measurement control signal and the output terminal of the synchronization trigger signal are N
Connected to the external reference clock input terminal, measurement control signal input terminal, and synchronization trigger signal input terminal of the o.2 slave unit, the external reference clock output terminal and measurement control signal output of the No. 2 slave unit The terminal and the output terminal of the synchronous trigger signal are connected to the external reference clock input terminal, measurement control signal input terminal and synchronous trigger signal input terminal of the No. 3 slave unit. It is connected.

Note that the measurement enable signal AEN is a signal indicating a measurable state and is output from all the devices connected in parallel, but is enabled when output from all the devices is completed. The measurement start signal AST is input from the master unit to each slave unit after the AEN signal is enabled. Each slave unit starts measurement by receiving the AST signal. The trigger enable signal TEN is a signal indicating a trigger waiting state, and is output from all devices connected in parallel, but is enabled when output from all devices is completed.

 The operation in such a configuration is as follows.

1) Operation of master unit An internal reference clock is selected as a time base clock, and this is also given to each slave unit. A / D converter 2
The internal reference clock or a frequency-divided version thereof is used as the sample clock.

After the AEN signal is enabled, the AST signal is sent, and measurement starts at the same time. After the TEN signal is enabled, the TRGEN signal is enabled, the trigger control circuit 5 is set to the operating state, and an individual trigger signal input thereafter is received, and this is output to each slave unit as a synchronous trigger signal.

2) Operation of slave unit The clock input from the master unit is used as the time base clock, and is transmitted to the subsequent slave units.
As the sample clock of the A / D converter 2, this clock or a clock obtained by dividing this clock is used. The measurement operation starts after receiving the AST signal input from the master device. The received AST signal is also sent to the subsequent slave units. As a trigger signal, a synchronization trigger signal input from the master unit is received and transmitted to the subsequent slave units.

According to this relationship, a common reference clock is supplied to each A / D converter, and the frequency is individually divided by each A / D converter. Can do it. Further, the trigger is invalid until all the devices are in the trigger waiting state, and the trigger function is valid only for the master device. The trigger timing of each slave device coincides with the trigger timing of the master device.

The measurement operation in each A / D converter starts simultaneously when all the devices can be measured. The end timing of the measurement operation can be set independently, and the data length of the data memory 3 can be set arbitrarily. it can.

<Problems to be Solved by the Invention> However, in a case where a plurality of A / D converters are operated in parallel, an input signal sampled at the timing of a strobe pulse first entered after the start of measurement can be handled as first data. For this purpose, it is necessary to provide a means for notifying that all the A / D converters operating in parallel are in a measurable state, and a means for determining that a strobe pulse input before the measurable state is invalid. However, the apparatus shown in FIG. 7 has a problem that it is not provided.

The object of the present invention has been made in view of such a point, and when an arbitrary number of units are operated in parallel with the same configuration, all of them are sampled at the timing of a strobe pulse which first enters after the start of measurement. It is an object of the present invention to provide an A / D conversion device that can handle as a first data.

<Means for Solving the Problems> According to the present invention for achieving the above object, one of an internal reference clock, an externally supplied external clock, and an external reference clock is selected and used as an external reference clock. Along with outputting to the outside, the selected clock is frequency-divided through a frequency divider, and then output to each of the internal parts, and the clock is enabled only when the signal indicating the measurable state is enabled. A sample clock generating circuit having a function of determining whether or not an external clock is input when the signal to be indicated is in a disabled state and outputting the result; and an analog input signal according to a clock provided from a frequency divider of the sample clock generating circuit. A / D converters that convert digital signals into digital signals, and any number of A / D converters with the same configuration during parallel operation Exchanges multiple measurement control signals between
Along with controlling the data storage operation of the data memory in accordance with these plurality of measurement control signals, and based on the signal indicating that it is in a measurable state generated from the sample clock generating circuit and each A / D converter, A data memory control circuit having a function of generating and receiving a signal indicating that the A / D conversion device is in a measurable state, and an arithmetic control unit for integrally controlling these units.

<Operation> When a plurality of A / D converters of the present invention are connected in parallel to perform analog-to-digital conversion, the start timing of A / D conversion of each device can be made uniform. Therefore, measurement with high time resolution is possible.

In addition, since the trigger operation between the devices can be controlled in association with each other, measurement with a high degree of freedom can be performed by a combination of arbitrary trigger operations.

Further, a signal (ARM) indicating a measurable state is generated from the data memory control circuit, and it is determined from the sample clock generating circuit whether or not an external clock is input when the signal indicating the measurable state is disabled. Since the signal (ILC) indicating the result is generated, the data sampled immediately after the start of the measurement during the parallel operation of the A / D converter can always be handled as the first data.

<Example> Hereinafter, the present invention will be described in detail with reference to the drawings. FIG. 1 is a principle configuration diagram showing an embodiment of an A / D converter according to the present invention. 7, the same parts as those in FIG. 7 are denoted by the same reference numerals. What is different from FIG. 7 is a signal ARM indicating a measurable state and a signal ILC indicating whether or not an external clock is input when the ARM signal is disabled.
And a write clock WCK for the data memory 3.

The data memory control circuit 4 outputs the ARM signal to the sample clock generation circuit 1 and the outside. The ARM output to the outside is an enable signal for the external reference clock.

On the other hand, the sample clock generation circuit 1 prevents a malfunction at the time of taking in data by validating only the clock when the ARM signal is enabled. Then, it determines whether or not an external clock is input when the ARM signal is in the disabled state, and outputs a signal ILC for outputting the result to the CPU 6.

FIG. 2 is a block diagram showing a specific example of FIG. In the figure, CLKIN is a sample clock generation circuit 1 of the preceding device.
, And CLKOUT is an external reference clock supplied to the sample clock generation circuit 1 of the subsequent device. AENS 'is a signal indicating a measurable state given from the data memory control circuit 4 to the data memory control circuit 4 of the succeeding device, and is wired-OR-coupled to the signal AENI indicating the measurable state of the input via the transistor Tr1. AENI and AENO are signals indicating the measurable state of all the A / D converters connected in parallel.Since each device is similarly connected to the collector of the transistor Tr1, the AENS ′ signals of all the devices are It is enabled only when it is enabled. ASTS is a measurement start signal output from the data memory control circuit 4 of the preceding device to the data memory control circuit 4 of the subsequent device, and is one input of the selector 8. ASTI is input from the data memory control circuit 4 of the preceding device to the selector 8 of the succeeding device. The ASTR signal is a measurement start signal input to the data memory control circuit 4 of each device via the selector 8, and receives an ASTS signal when operating as a master device and an ASTI signal when operating as a slave device. Is entered.

ASTO is a measurement start signal output to the subsequent device, and the same signal as the ASTR signal is output via the selector 8.
TENS 'is a signal indicating a trigger waiting state output to the subsequent device and output via the transistor Tr2. T
ENR is a signal input from the data memory control circuit 4 of the preceding apparatus to the data memory control circuit 4 of the succeeding apparatus and indicating a trigger waiting state, and is applied to the collector of the transistor Tr2 of the succeeding apparatus. TENI and TENO are signals indicating a trigger waiting state of all the A / D converters connected in parallel.Because these TENI and TENO are connected to the collector of the transistor Tr2, the TENS ′ signals of all the devices are output. It is enabled only when it is enabled.

MSIDI is a set operation mode identification signal input from the preceding device to the succeeding device. When the device is set to operate as the master device, it is at the H level, and when the device is set to operate as the slave device. Becomes L level. MSIDO is a set operation mode identification signal output from the preceding device to the succeeding device, and the end of the signal line is connected to the common potential point.

TRGEN is a signal indicating a trigger standby state output from the data memory control circuit 4 to the trigger control circuit 5 in each device, and TRIG is a trigger signal input from the trigger control circuit 5 to the data memory control circuit 4. TRGI is a synchronization trigger signal input from the trigger control circuit 5 of the preceding apparatus to the trigger control circuit 5 of the succeeding apparatus, and TRGO is a synchronous trigger signal output from the trigger control circuit 5 of the preceding apparatus to the trigger control circuit 5 of the succeeding apparatus. Signal.

FIG. 3 is a block diagram showing a specific example of the sample clock generation circuit 1 of FIG. Reference numeral 9 denotes an internal reference clock generation circuit that outputs an internal reference clock INTCLK, reference numeral 10 denotes a switch for selecting the internal reference clock INTCLK, external clock EXTCLK, and external reference clock CLKIN, and reference numeral 11 denotes a clock for selecting the clock selected by the switch 10 to a desired value. This is a frequency divider that circulates and outputs the signals to various internal parts. Reference numeral 12 denotes an edge trigger type flip-flop. An inverted signal of an ARM signal is applied to a D input terminal, and an external clock EXTCLK is applied to a clock terminal. 13
Is an AND gate for ANDing the ARM signal and the EXTCLK signal.

In such a sample clock generation circuit, the external clock is valid only when the ARM signal is enabled. When an external clock is input while the ARM signal is disabled, the flip-flop 12 outputs an ILC signal. The ILC signal is read by the CPU, and it is determined whether or not an external clock is input before a measurable state is obtained, and the result is displayed on a display device (not shown). This allows
It is possible to inform whether or not data sampled at the first clock input after the start of measurement is treated as the first data in the memory.

FIG. 4 is a block diagram showing a specific example of the trigger control circuit 5 of FIG. 14 is individual trigger signal and synchronous trigger signal TRGI
The switch 15 selects the time difference between the trigger signal output from the switch 14 and the time at which the analog input signal (trigger point data) at the trigger time is converted into a digital signal by the A / D converter 2 and output. Is a timing control circuit that outputs the trigger signal TRIG to the data memory control circuit 4 after the correction of the above. The output of the switch 14 is output to the subsequent device as a synchronization trigger signal TRGO.

The operation of the device configured as described above will now be described. The basic measurement operation is the same as the operation described in the conventional example. FIG. 5 is a time chart showing the operation at the start of measurement by itself. When the measurement start command signal START is output from the CPU 6, AENS 'is at H level (disabled state).
To an L level (enabled state). AE
NR changes from L level (disable state) to H level (enable state). ARM is triggered by the rise of this AENR
Goes from L level (disabled state) to H level (enabled state).

The ARM signal is disabled by the next rising edge of START. When the ARM signal is in the disabled state, the external clock is canceled, and the external clock is accepted only when the ARM signal is enabled.

When an external clock is input while the ARM signal is disabled, the flip-flop outputs an ILC signal at the rise of the external clock. ILC signal is CPU6
When the ILC signal is enabled, it is determined that the external clock has been input prior to the start of the measurement, and the fact is displayed.

With the above operation, the external clock input after the start of the measurement and the measured data are temporally different from each other by inputting the external clock with the rising edge of the ARM signal as a trigger.
It will correspond to one to one. That is, data sampled by the nth input external clock is handled as the nth measurement data.

FIG. 6 shows a time chart at the start of the measurement in the parallel operation. The CPU 6 of each device outputs a START signal independently, whereby AENS 'is also output at a different timing for each device. The AENR of each device is simultaneously enabled in synchronization with the generation of the latest AENS 'signal. When the AENR signal is enabled, the ARM signal is enabled and the system enters an external clock waiting state.

The ARM signal is in a disabled state from when the START signal is output from the CPU 6 until the AENR signal is enabled. During this time, the ARM signal is canceled even if an external clock is input. At this time, a signal ILC indicating that an external clock has been input before the start of measurement is output. Subsequent operations are the same as in the single measurement.

<Effects of the Invention> As described in detail above, the present invention has the following effects.

When operating the A / D converter with an external sample clock, a signal indicating the start of measurement is output to the outside of the A / D converter,
By inputting an external sample clock using the signal as a trigger, a temporal correspondence between the input external sample clock and the measurement data can be obtained. That is,
Data sampled by the n-th external sample clock can be handled as the n-th measurement data.

Further, by canceling the external clock input before the start of the measurement, the correspondence between the sample clock and the measurement data is prevented from being broken.

Furthermore, by outputting a signal indicating that an external clock is input before the start of measurement, it is possible to indicate that the input timing of the sample clock was inappropriate, and thus, the input timing of the external clock was input before the start of measurement. It can be seen that the data is not sampled by the external clock.

[Brief description of the drawings]

FIG. 1 is a block diagram showing the principle of an embodiment of an A / D converter according to the present invention, FIG. 2 is a block diagram showing a specific example of FIG. 1, and FIG. 3 is a sample clock generating circuit of FIG. FIG. 4 is a block diagram showing a specific example of the trigger control circuit of FIG. 2, FIG. 5 is a time chart showing an operation at the start of measurement by itself, and FIG. 6 is a parallel operation. FIG. 7 is a diagram illustrating the principle of the conventional A / D converter, and FIG. 8 is a diagram illustrating the parallel connection state of the A / D converter of FIG. DESCRIPTION OF SYMBOLS 1 ... Sample clock generation circuit 2 ... A / D converter, 3 ... Data memory 4 ... Data memory control circuit 5 ... Trigger control circuit, 6 ... CPU 7 ... Bus, 8 ... Selector 9 ... ... internal reference clock generation circuit 10 ... switch, 11 ... frequency divider 12 ... flip-flop, 13 ... AND gate 14 ... switch 15 ... timing control circuit

──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H03M 1/00-1/88

Claims (1)

(57) [Claims] An internal reference clock, an externally applied external clock and an external reference clock are selected and output to the outside as an external reference clock, and the selected clock is passed through a frequency divider. The clock is valid only when the signal indicating the measurable state is enabled, and the clock is enabled only when the signal indicating the measurable state is enabled, and whether or not the external clock is input when the signal indicating the measurable state is disabled. A sample clock generation circuit having a function of judging and outputting the result; an A / D converter for converting an analog input signal into a digital signal according to a clock supplied from a frequency divider of the sample clock generation circuit; During parallel operation with a number of A / D converters, a plurality of measurement control signals are transmitted and received between In addition to controlling the data storage operation of the data memory according to the signal, all A / D conversions are performed based on the signal indicating that the sample clock generation circuit and each A / D converter are in a measurable state. An analog-to-digital conversion device comprising: a data memory control circuit having a function of generating and receiving a signal indicating that the device is in a measurable state; and an arithmetic control unit for integrally controlling these units.