SU1140126A1 - Microprocessor - Google Patents

Abstract

A MICROPROCESSOR containing a microprogram control block, a microinstructions memory block and an operating block, the transfer output of the operation block connected to the signs input of the microprogram control unit whose feature output is connected to the transfer input of the operation block whose input of the operation code is connected to the output of the microoperations code of the memory block microinstructions, the output of the masking code of which is connected to the mask input of the operating unit, the output of the address of accessing the data memory of which is the address output m microprocessor, microprocessor information output connected to the information output of the operating unit, the first and second information inputs of which are respectively the first and second information inputs of the microprocessor, the outputs of the control code - the formation of the address of the next microcommand and the flag control code of the microprocessor memory block are connected respectively to the control inputs address and control of the entry and storage of the flags of the microprogrammed control unit whose address output is With an address of the microinstructions memory block, the instruction code entry of the microprocessor control block is an input of the microprocessor instruction code, characterized in that, for the sake of speed, ok contains a controlled synchronizer that contains three pulse formers, an element NOT, an element 2I -OR-NOT and r (clock pulse pulse, whereby the output of the sign of the transition of the microcommand memory block is connected to the first input of the 2I-OR-NOT element and to the control input of the clock pulse, the first, second and third outputs connected to the inputs of the first, second and third pulse shapers, the outputs of which are connected respectively to the second and third inputs of the element 2I-Ш1И-НЕ and with the input element NO, the output of which is connected to the synchronization input of the operating unit, the output of element 2I-OR- NOT connected to the sync input of the firmware control block.

Description

11 The invention relates to computing technology, in particular microprocessor-controlled microprocessor systems, used, for example, to process radar signals. A microprocessor is known that includes a microprocessor control unit, a microinstructions memory block, an operational block L, In this microprocessor, a microcommand is sampled from the microinstruction memory block and the microcommand is executed by the operating unit sequentially during a clock cycle, which increases its duration. The closest to the present invention is a microprocessor containing a microprogram control unit, a microinstructions memory unit and an operation unit, the transfer output of the operation unit connected to the input of the signs of the microprocessing control unit, the output of which features are connected to the transfer input of the operating unit whose input of the operation code connected to the micro-operations microcode operation code output, the output of the masking code of which is connected to the mask input of the operating unit, the address of the access address and the memory nnyh which is the address output of the microprocessor, the microprocessor Inforga mation output coupled to the data output of the operation unit, the first and secondary cluster information vhodykotorogo are respectively first and. the second information inputs of the microprocessor, the outputs of the control code for the flags and the control code for the formation of the address of the next microcommand of the microcommand memory block are connected respectively to the control input by storing and storing the flags and controlling the address of the microprogrammed control block whose address is connected to the address input of the memory block These microinstructions, the input to the instruction code of the firmware control block is the input to the instruction code by the microprocessor. In this microprocessor, the pipeline register delays the micro-command selected in the current clock from the microinstructions memory block until the beginning of the next 62 clock. On the other hand, with the beginning of the next clock cycle, the next microcommand from the microcommand memory block begins sampling. Thus, partial overlapping of the time of the next microcommand from the microcommand memory block and the previous microcommand in the operational block occurs. This shortens the cycle time 2. However, since the execution of the microcommand is delayed until the next clock cycle, the execution of conditional transitions according to the results of the microcommand is also delayed accordingly. Thus, this microprocessor requires two cycles to perform a conditional transition, which leads to an increase in the execution time of the microprograms and to a decrease in the usable capacity of the microcommand memory block, some of which need to be filled with empty microcommands (arriving at the second time step of the conditional transition). In addition, the duration of the cycle includes the time of recording information in the pipeline register, which slightly increases the duration of the cycle. I. The purpose of the invention is to increase speed. The goal is achieved by the fact that a microprocessor containing a microcommand memory block, a microprogram control unit and an operation block, the transfer output of the operation block is connected to the input of the signs of the microprogram control unit, the output of which signs are connected to the transfer input of the operation block, the input of the operation code of which is connected with the output of the micro-operations micro-operations code, the output of the masking code which is connected to the mask input of the operating unit, the output of the address of the memory address access The output of which is the microprocessor address output, the microprocessor information output is connected to the information output of the operation unit, the first and second information inputs of which are respectively the first and second microprocessor information inputs, the outputs of the control code of the next microcommand and the control code of microcommands connected, respectively, with the inputs for managing the address and controlling the entry and storage of the flags of the microprogrammed control unit The address output of which is connected to the address input of the microprogram memory block, the instruction code entry of the microprocessor control block is the input of the micro-command command code, a controllable synchronizer is inputted, holding the three pulse makers, the HE element, 2I-SH-HE, and the clock generator pulses, the output of the sign of the transition of the microinstructor memory block is connected to the first input of the element 2И-ИИ-Не and to the control input of the clock generator, the first, second and third outputs of which are connected respectively to the inputs and the first, second and third pulse formers, the outputs of which are connected respectively to the second and third inputs of the 2I-OR-NOT element and to the input of the NOT element, the output of which is connected to the synchronization input of the operating unit, the output of the 2I-OR-NOT element is connected to the input synchronization of the firmware control block. Fig, 1 shows a functional microprocessor circuit; in fig. 2 - time diagrams of the microprocessor; in fig. 3 - block scheme of the microprocessor functioning algorithm. The microprocessor contains block 1 of memory of micro-commands, block 2 of microprogram control, operational block 3, generator A of clock pulses, element 2I-OR-NOT-5, pulse former 6, 7 and 8 and the element NOT 9. Consider the operation of the microprocessor (Fig . one). The microprogram is stored in the microcommand memory block 1. The microprogram control unit 2 controls the selection of microcommands from block 1 by the control signal of the address of the next microcommand (A) from the output of block 1 to the corresponding input of block 2. In addition, the microcircuit sample. The mand can control the signal from the input of the microprocessor command (KOM), which arrives at the corresponding input of block 2. Based on the command code of the KOM unit 2 generates the address of the first micro 264 command from the sequence of microcommands that implement this command. Therefore, the start of the microprocessor, i.e. Sampling the first microcommand of the first command is carried out on the basis of the state at the input of the COM of block 2. In the process of executing the command, the transition to the next microcommand is carried out according to the state at the input of the UA of block 2. Block 2 performs flag operations, i.e. entering and storing the states at the input of the signs (F1), and also controls the state at the output of the signs (FO) by the flag control signal (UV) coming from the corresponding output of block 1. Sampling the next microcommand is performed by the formation of address 2 by the block (A ) regular microcommand; This address is sent to the address input (A) of unit 1. The microinstructions outputs (F) and the mask code (K) of block 1 are connected to the corresponding inputs of the operating unit 3. The signals on these inputs determine the type of nickname instructed to block 3, the choice of inputs (V) or (M) as a source of input information. Operational unit 3 has a transfer input (CO) connected to the output of unit 2, and a transfer output (C1), which is used as a sign when performing conditional transitions. The output 01 of block 3 is connected to the input of the characteristic of block 2. The output of the transition flag (PP) of the microcommand memory block 1 is connected to the control and input of the clock / h generator and to the first input of element 2I-OR-NOT 5. For the generation of clock pulses of the required duration for blocks 2 and 3, three pulse formers 6, 7, and 8 are used. Element 2I-OR-NE 5, on the first output signal, outputs the output connected to the synchronous input () of block 1, or two synchro impulses or one (per microprocessor operation cycle) . Element 9 is used to match the logic of the sync pulse with the logic of the clock input () of the operation unit 3. In the dynamics, the microprocessor operates as follows (Fig. 2 and 3). According to the code at the KOM input, the microprogram control unit 2 generates the address A of the initial microcommand; this microcommand is selected from the microcommand memory block 1 and appears at its outputs. From this moment begins the first cycle of the microprocessor. Clocks with unconditional and conditional transitions differ from each other.

Consider a beat with an unconditional transition. The sign of the transition of the GSH in the microcommand is then programmed into the state log. 1. The signal from the output of the PP block 1 is fed to the control input of the generator 4, which outputs signals with a period T1 to its outputs. The pulses on the first, second and third outputs of the generator 4 have a phase shift C ,, and (/. On the leading edges of these pulses, the formers 6, 7 and 8 generate pulses with a duration of tuBMD, respectively, and the pulse of the formers 6 and 7 are fed to the second and third inputs element 2I-OR-NOT 5. Since at the first input of this element there is a signal of a sign of a PP transition, an equal log, 1, then both pulses pass through element 2I-OR-NOT 5 and arrive at the sync input Sem at the microprogram control unit 2, the first clock pulse unit 2 forms without the address of the next microcommand. For this, the sync pulse must start after the preset time t ,, control signal for generating the address of the UA. After some delay in the sync pulse, the code of the next address A appears on the output of block 2. From this moment the procedure of sampling the next microinstruction from microinstructions memory block 1, which will end in time tin.

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On the other hand, in parallel with the formation of the address A and block 2, the microinstruction F is decoded. in operation block 3. After the microinstruction F is decrypted based on the mask code K, the operation block 3 generates internal transfer signals from the lower order bits to the senior and most senior transfer, which is the transfer output C1. The total time of the formation of a reliable signal at the output C1 from the start of the clock cycle is denoted by t. After forming the transfer signals through time, the operation unit 3 can begin executing the microinstruction F. To do this, a sync pulse is fed to its sync input, the start of which is delayed from the beginning of the clock cycle for the time tt hours After the sync pulse on the buses F and K of block 3 has been stored, the time t., until the completion of all transients inside the operating unit 3. After the operating unit 3 has developed a signal at output C, it is possible to reliably carry out the recording and storage operations azhkov a microprogram control unit. These operations are reliably performed on the second clock pulse on Cg, .. The start of this clock must be delayed by the time tym of presetting the signal at the input of the F1 attribute of block 2. After this clock pulse is over, the state on the flag controls of the UV block 2 must be saved for time t (f) until the end of the transient processes in this block. In this way, three ways of propagation of signals in the microprocessor can be distinguished, which determine the duration of a cycle during an unconditional transition:

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delays from ,,, L., 2 and from generator 4 must ensure the time delays of all sync pulses relative to the start of the clock to the maximum preset time t, uu, t + + tLj (p, t + t (j (. Pulse drivers 6 , 7 and 8 provide the necessary duration of clock pulses.

Consider a clock with a conditional transition. The sign of the PP transition in the microcommand is then programmed to the log state. A. On the output signal of the PP block 1, the generator 4 enters the pulse shaping mode with a period of 12. The phase shifts of the output pulses of the generator 4 do not change: they are equal, t and t. Since the first input of element 2-OR-NOT 5 is the state of the log. Oh, coming from block 1, then through this element 5 does not pass liMiiyjibc with. the first driver 6a passes only a pulse from the second-driver driver 7. As a result, one i sync pulse is sent to the microprogram control unit 2. This clock has exactly the same delay t. + tllf relative to the start of the clock, as the second clock pulse in clock with unconditional transitions. Consequently, according to the considered sync pulse, the microprogram control unit can adequately perform the flag entry and storage operations, since the transfer signal is already generated by operation block 3. Thanks to the reliable transfer signal and the sync pulse on C, microprogram control 2 can generate a conditional sync pulse. i.e. dependent on the carry signal, the address of the next microcommand. After the termination of the sync pulse C, this conditional address A is delayed by block 2 with delay 2 and, after the sampling time .g, the microcommand memory 1 will issue a microand command, which is the first microcommand of one of the two program branches. In the next cycle, the execution of this microcommand will begin. Thus, the conditional transition occurred in one cycle. This clock has a longer duration compared to clock cycles with unconditional jumps to the amount of waiting for a reliable signal from the operating unit 3. However, it is always shorter than the two clock cycles of the prototype, in which micro-instructions are sampled twice, the same delays for signal presets repeat as in the proposed micro processor. The sync pulse to the operation unit 3 is delivered with the same delay t t, | C "as in the tact with unconditional transitions, t, e, the microinstructions are executed in both cases in the same way. In the considered tact, it is also possible to select three paths of propagation of signals that influence the duration of the cycle TC during a conditional transition: ijcft, - tj ,, + t + tug + t,.; T ,, one tj., + T (jc +. - t (., + T: (jqp + ty + tq The duration of the cycle will be equal to the greatest of these values. The duration of the cycle of the generator 4 during conditional transitions (i.e. by signal log, O on the control input) must be equal to Tcc, the other parameters of the controlled synchronizer are the same as in steps with unconditional transitions. As block 2 in the proposed microprocessor you can, for example, use a microprocessor control block from the K586 microprocessor sets, K589 series. To build the operating unit 3, you can use the central New processor elements and accelerated transfer schemes from any microprogrammable microprocessor set, for example, from the same K586, K589 series. Let us perform a numerical evaluation of the microprocessor speed in comparison with the prototype. Let the sampling time of information from the memory module of microcommands t.Q 40 HC. We will accept the base set K589 of the series, the width of the operating units of the prototype and the proposed microprocessor is 16, the time parameters in the case under consideration are ty 10 NS, tcrdy 30 NS, td b44ns, AQ С, t (. 72 not (this delay consists of the delay in the formation of the transfer preview signals by the central elements equal to 52 non and the response time of the accelerated transfer scheme equal to 20 non), tUF 15 non, tf-ip 20 NS, 27 HC, to (jg 33 non , tjy 5 NS. As a result, we get: (5L, 137 NS. Tooled 201, not, the minimum possible duration of a tact of the prototype is 162 ne. Thus, with unconditional transitions, the duration of a measure was reduced by 15%, with conditional (compared to two acts of the prototype duration of 162 nsx2 324 not) - 38%.

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Claims (1)

A MICROPROCESSOR comprising a microprogram control unit, a micro-command memory unit and an operation unit, the transfer output of the operating unit being connected to a feature input of the microprogram control unit, the feature output of which is connected to a transfer input of the operating unit, the operation code input of which is connected to the micro-operation code output of the micro-command memory unit, the output of the masking code of which is connected to the input of the mask of the operating unit, the output of the address of the access to the data memory of which is the address output of the micro of the processor, the information output of the microprocessor is connected to the information output of the operating unit, the first and second information inputs of which are the first and second information inputs of the microprocessor, the outputs of the control code · the formation of the address of the next microcommand and the control code of the flags of the micro memory unit are connected respectively to the inputs address management and control of entering and storing flags of the microprotogram control unit, the address output of which is connected to the address the input of the memory block of microcommands, the input of the code of the command of the block of microprogram control is the input of the code of the command of the microprocessor, characterized in that, in order to increase the speed, it contains a controlled synchronizer containing three pulse shapers, an element NOT, an AND-OR-NOT element, and a generator clock pulses, the output of the transition indication of the micro-memory block being connected to the first input of the 2I-IPI-NOT element and to the control input of the clock pulse generator, the first, second and third outputs of which are connected respectively it is with the inputs of the first, second and mA of the third pulse shaper, the outputs of which are connected respectively ”but with the second and third inputs of the element 2I-OR-NOT and with the input of the element NOT, the output of which is connected to the synchronization input of the operating unit, the output of the element 2I -OR- NOT connected to the synchronization input of the firmware control unit. 1