SU1228096A1 - Information input device - Google Patents

Abstract

The invention relates to the field of information technology and can be used in digital systems for collecting and processing analog information. The aim of the invention is to expand the functionality by providing simultaneous input of information and a data processing program and organizing more economical memory utilization and computing power of a digital computer, which consists in reducing the memory volume of the digital computer used by the pre-processing programs of input signals, as a result of which increases the number of objects serviced by this digital computer while maintaining its computing power. The device contains a switch, an analog-to-digital converter, a buffer register, a control unit, an interfacing unit, a memory unit. The solution of this goal is provided by organizing a control unit that contains an address register, an address decoder, a command register, a command decoder, an operation control register, an OR-NOT element, an AND element, a controlled frequency divider. c (O SL

Description

The invention relates to automation and computing and can be used in digital systems for collecting and processing analog information.

The purpose of the invention is to enhance the functionality by providing simultaneous input of information and a data processing program.

The drawing shows a block diagram of the proposed device.

The device for inputting information contains a switch 1, an analog-to-digital converter (ADC) 2, a buffer register 3, an interface block 4, a memory block 5, a control block 6 containing an address register 7, an address decoder 8, a command register 9, a decoder for 10 commands, a mode control register 11, an element OR NOT 12, an element AND 13, a controlled frequency divider -14.

The device is working. in the following way.

All operations are synchronized by signals arriving at the first input of the device. A command is sent to the inputs of the memory unit and the interface unit, which consists of the input device address, the analog input address and the code for the length of the interrogation zone and prepares the interface unit for operation. The device access command enters the interface unit, while the interface module receives the command part that contains the address of the input device. The address combination is recognized in the interface block, as a result, the code of the analog input address is written to the address register 7. In addition, this signal permits access to memory block 5 and is a control signal. If there is an active signal from the interface unit, the device switches to the operation mode with control from memory unit 5. For each analog input, a memory element is allocated, whose address is determined by the address of the corresponding, analog signal input. Inside the element, an auto-incrementing addressing method is used. An increase in the content of the element is performed on the sync signals. The corresponding element of the memory block 5 contains the commands to start the A / D converter 2, write the result of the conversion to the buffer register and transfer, and allow polling the inputs.

switch, as well as the commands necessary for intermediate data processing.

Information relating to the management of the input device and stored in the memory unit is supplied to the control unit 6 and to the command register. In this register, the codes for the ADC start and polling of the switch inputs are entered into the register. Three modes are possible: addressable, cyclic, address-cyclic, when the switch inputs are polled alternately within a certain zone defined

5 boundary addresses. Of these modes, you can set the length of the interrogation zone, the address mode corresponds to the zero zone, and the cyclic mode has the interrogation zone, the length of which is equal to the number of switch inputs. The length of the interrogation zone, represented by a reverse code, is entered into register 11. At the next cycle, the command to start the ADC is read from the memory unit — from 5, element E 13 is hidden, through which the clock pulses arrive at the input of register 17. The number of pulses necessary to completely fill register, obviously equal to the polling zone.

Q At the same time, the output of the OR-NOT element will be high potential, which ensures the opening of the element AND 13 and the passing of clock signals to the summing inputs of registers 7 and 11 for all combinations except those containing all units. The last combination will take place in the polling of all the inputs of the switch within the specified polling zone. The pulses arriving in register 7 change its contents, ensuring a sequential change in the addresses of the inputs of the switch. Obviously, cyclical polling of inputs is the opposite of the previous one.

Due to the fact that the data processing programs arriving at different inputs may have different lengths in cyclic and address-cyclic modes, the interrogation rate of the switch inputs must be matched to the time required to transfer the necessary programs and data from the memory block for This clock signal is received in registers 7 and 11 through a controlled frequency divider 14. The division factor control is performed by the switch input address code stored in register 7.

five

0

0

This code is decoded by decoder 8, the output of which is used to control the switch and set the desired gain of the ADC amplifier. The output signals of the controllable divider are also used to start the A / D converter. On signal, the conversion end generated by the A / D converter is converted into a buffer register, from which, at the right time, determined by the memory block command, goes to the output of the device. Data of the memory block is also received via the same path.

The proposed device allows more economical use of computer memory by reducing the amount of computer memory occupied by input management and intermediate processing programs, as a result of which the number of serviced analog objects can be increased without an increase in computer memory.

Claims (1)

Invention Formula . A device for inputting information containing a channel switch, an analog-to-digital converter, a buffer register, a coupling block,. the memory block, the inputs of the memory block and the interface block are the inputs of the first group of the device, the input of the interface block is the first input of the device, the output of the interface block is connected to the second input of the memory block, the outputs of the group of the interface block and the outputs of the block the memory is connected to the inputs of the first and second groups of the control unit, respectively, the outputs of the group of the control unit are connected to the address inputs of the switch and to the inputs of the analog-digital converter group, the information inputs of the switch are the inputs of the second group The device, the switch output is connected to the first input of the analog-digital converter whose outputs are connected to the information inputs of the buffer register, and the output connected to the third input of the control unit and to the first control input of the buffer register, the information outputs of which are the outputs of the second group device, the first output of the control unit is connected to the second input of the analog-to-digital OBOB converter, which is so that, in order to expand its functionality by providing neous data input and a data processing program, a first input of the control unit and a first input of a memory unit connected to the five first input device, the output interface unit is connected to the second input of the control unit and is output apparatus outputs groups of the memory block are outputs of the first group of the device, the second output of the control block is connected to the second control input of the buffer register, the control block contains the address register, address decoder, command register, command decoder, control mode control register, OR element NOT element , controlled frequency divider, inputs The address register groups are the inputs of the first group of the control unit, and the outputs are connected to the inputs of the controllable frequency divider group and address decoder, the outputs of which are the outputs of the control unit group, the inputs of the command register register and the control mode control register , the outputs of the command register are connected to the inputs the command decoder, the first and second outputs of which are the second and first outputs of the control unit, the third output is connected to the input of the address decoder, the fourth output is connected to the first input of the AND element, the command register input is the third input of the control unit, the first control register input is the second input the control unit, and the outputs are connected to the inputs of the OR-NOT element, the output of which is connected to the second input of the AND element, the third input of which is connected to the output of the controlled frequency divider, whose input is the first input of the control unit, the output of the AND element is connected to the input of the address register and the second input of the mode control register. Editor Y. Sereda Compiled by V. Bazovkin Tehred G.Gerber Proofreader A. Ferenc Order 2303/49 Circulation 671 Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhgorod, st. Project, 4