SU1399746A1 - Device for interfacing computer with communication channels - Google Patents

Abstract

The invention relates to the field of computer technology and can be used in telecommunication computer systems. The aim of the invention is to improve the speed. The device contains a communication node 1, an encoder 2, a buffer memory 3, a decoder 4 of control of channel switching, a counter 5, a decoder 6 of register polling, triggers 8, 9, 13, a group of 10 control registers, a group of 17 decoders, a delay element 16, elements AND P, 14, 15, elements OR 12, 18, 19. 1 or g

Description

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The invention relates to computing and can be used in telecommunication computing systems.

The purpose of the invention is to increase the speed of the device.

The drawing shows a diagram of a device for interfacing a computer with communication channels,

The device contains the node 1 of the 1SCH switch, the encoder 2, the buffer memory 3, the decoder 4 of the control of channel switching, the counter 5, the decoder of the polling b., Registers, the decoder 7 addresses, the second 8 and the first 9 triggers, the group of registers 10 of control, the first element I 11, the third element OR 12, the third trigger 13, the three element I 14, the second element 15 and 15, the delay element 16, the decoders 17, the second 1B and the first 19 elements OR, as well as the inputs and terminals 20–25.

The device works as follows

Shift registers are used as control registers 10. The interrogation of the positional bits of each of the control registers is performed by successively shifting the recorded code when applying clock pulses to their synchronization. Thus, the information outputs of the control registers during polling sequentially

the information recorded in them is repeated

matsi Upon completion of the survey, all positional bits of the corresponding control register 10 are written with zeros. This results in the output of the corresponding decoder 17 signal, which through the OR 19 element goes to the control input of the polling request of the decoder 6 poll of registers and the second information input of the decoder 4 control channels switching, When the decoder 6 polling registers connects for polling the following options, control register 10, - and the switch control decoder 4 provides the connection through the node 1 comm the next channel uatsiya SVYAIp

Each of the control registers 10 corresponds to a specific communication channel number, and each positional position contains a page and a buffer memory, 3, All bits of each of the control registers 10 are sequentially polled using the decoder 6

with

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sa registers. The polling order of the decoder control registers 10 is determined according to their priority and in order of numbering. When recording information in the exchange mode, the code corresponding to the exchange mode over a certain channel is written to each of the control registers 10. For example, if J contains in the buffer memory 3 pages for M communication channels, then the number of control registers must be equal to M, and the bit Each of the control registers must be equal to K, with each M th control register being allocated by node 1. as belonging to the exchange mode in only one channel: information is read into one buffer channel in all buffer states, which correspond to Vival units in a certain control register 10. The connection of one or another page of the buffer memory is carried out through the address decoder 7. Message conversion is performed by encoder 2 by clock pulses.

In the information exchange mode, the device access signal arrives at trigger 9. A clock pulse through elements 11 and 15 enters the decoder 6 of register polling and polls the first bit of the corresponding control register 10. If O is recorded in this bit of the polled register, then the state of the device elements does not change and the next clock pulse arrives at polling the next bit of this register 10. If 1 is written, the signal from the polled register 10 goes through OR 18 to the decoder 7 addresses to connect the corresponding page of the buffer memory and through the OR element 12 switches the trigger 13 to the zero state 1SH While the following clock pulses through the delay element 16 and the AND 14 linear element: go to counter 5, From the output of the counter 5 signals ly are input to encoder .. After completion of the conversion the message output from the counter 5 is removed overflow signal which via the AND gate 12 toggles flip-flop 13 in a single state.

Element And 15 opens, and the clock pulses again begin to flow through the decoder 6 poll polls

to poll the following bits of this register 10 control. The transition to polling the bits of the next register 10 of the control group is carried out in the following cases:

The survey of all bits of the corresponding control register was completed (the last bit of the control register under consideration was one);

completed the survey of all bits of the corresponding control register in which the units were contained (the remaining last bits of the control register under consideration contain zeros);

all bits of the corresponding control register contain zeros (in accordance with the exchange mode code, the transmission of information in a communication session on this channel is not provided).

In all these cases, in the corresponding control register 10, all positional bits as a result of polling (the first and second cases) or as a result of writing the zero code of the exchange mode (the third case) are zero and therefore there are also zeroes on its bit outputs. Therefore, the zero state of the register corresponds to the signal at the output of the decoder 17 connected to its bit outputs.

In this way, all the group control registers 10 are sequentially polled and information is sent to the corresponding channels from the specified pages of the buffer memory. In the information receiving mode, the trigger 8 operates, which via the decoder 4 connects the communication channels to the encoder 2. The information is written to the buffer memory also in accordance with the information on registers 10 of the control about the exchange rate. Upon the completion of the reception or transmission of information from the exit output of the poll to the decoder 6 of the register polling, a signal is taken which arrives at the trigger 9 and brings it to the zero state. In this case, the Ready signal is generated at the output 25. Thus, when accessing the device, the control bits are polled with clock pulses. If O is read from the control registers in this case, then the next interrogation signal is

five

a rare clock pulse, if 1, then the next interrogation signal is formed at a time interval equal to the page conversion time. Moreover, if the polling of all bits of the corresponding control register of the group in which the units were contained is completed, and the remaining bits of this register contain 0, then the transition to the next bits of the next register of the control register is carried out. Also, the decoder 6 is switched to polling the next 5 by priority (number) of the control register without polling the position-bits of the next control register, if in accordance with the exchange mode code the information in the communication session on the corresponding channel is not provided ( O) is recorded in all positional bits of this register.

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Claims (1)

Invention Formula 25 thirty Device for interface of computer with communication channels, containing switching node, encoder, buffer memory, address decoder, channel switching control decoder, three triggers, counter, three AND elements, first OR element, group 35 reg of the control sources, with the first information input and output of the switching node being the input and output of the device for connecting to the communication kayal, the first information input and 40, the output of the buffer memory is the input and output of the device for connecting respectively to the information output and input of the computer, the first input of the first element I is 45 the input of the device for connecting to the clock output of the computing one. the machines, the unit input and the zero output of the first trigger are the input and output of the device for connecting 50 respectively, at the output and readiness of the computer, the single and zero inputs of the second trigger are the device inputs for connecting to the write and read outputs of the computer, the information inputs of the group control registers form a group of device inputs for connecting the computer to the address outputs of the computer. In this case, the information output of the circuit-switched control decoder is connected to the control input of the switching node, the second information input and output of which are connected respectively to the first information input and input of the encoder a, the second information input and output of which are connected respectively to the second information output and input the buffer memory, the address input of which is connected to the output of the addressfixer, the unit output of the first trig-irepa is connected to the second input of the first element I, the output of which is Inen with the first input of the second element I, the second input of which is connected to the single output of the second trigger, the output of which is connected to the first input of the third element I, the output of which is connected to the counting input of the counter, the output of which is Encoder's enable input, second trigger steering output is coupled to the channel switching control decoder input, characterized in that, in order to improve speed, a decoder group, a poll polling decoder, a delay element, two and the element OR, while the zero input of the first trigger is connected to the output of the poll polling decoder, the output group of which is connected to the synchronous inputs of the corresponding control registers, the information outputs of which are connected to the input group of the second element OR, the code of which is connected to the information input of the address decoder, to the first input of the third element AND the first information input of the circuit switching control decoder, the second information input of which is connected to the control input of the register poll decoder with the output of the first OR element, the group of inputs of which is connected to the outputs of the grztpa decoders, the information input groups of which are connected to the information output groups of the corresponding control registers of the group, the counting input of the third trigger is connected to the output of the third OR element, the second input is connected to the transfer output of the counter, the input of the third element And is connected to the output of the delay element, the input of which is connected to the output of the first element And, the output of the second element And is connected to the information input om the register polling decoder.