SU1347173A1 - Multichannel delayed pulse generator - Google Patents

Abstract

The invention relates to control devices for complex objects and can be used in automated systems for the identification of electrophysical objects. The aim of the invention is to extend the functionality by delaying a series of pulses and simplifying the device. To achieve this goal, a multiplexer 4, an adder 6 and a multiplexer 7 are added to the device, and the storage device is made in the form of a random access memory (RAM) 5. In addition, the device contains a generator 1 of the reference frequency, counter 2, latch 3 zero level, output pulse shapers 8.1-8. P, where n is the number of delay channels determined from formula n 2 - 1, where m is the number of least significant bits selected from the condition m logj, n. In order to eliminate the possibility of generator malfunction due to the finite number of RAM 5 cells, it is necessary to select the corresponding width of counter 2 and RAM 5 so that the information in this cell is updated only after reading the previous information. 3 il. i (Л С со со J co

Description

The invention relates to control devices for complex objects and can be used in automated systems for the identification of electrophysical objects.

The aim of the invention is to extend the functionality by the possibility of delaying the pulse train and simplifying the device.

FIG. 1 shows the structural scheme of the proposed generator; in fig. 2 shows diagrams explaining his work; FIG. 3 - shaper output pulses.

The multichannel generator of delayed pulses consists of 1 reference frequency generator, counter 2, zero level clamp 3, multiplexer 4, random access memory (RAM) 5, adder 6, demultiplexer 7, and shapers 8.1-8. The output pulses, where n 2 - 1 - the number of delay channels.

The generator 1 of the reference frequency is connected by its output to the input of summing counter 2 and the resolution enable input of RAM 5. The output bus of the lower-order bits of counter 2 is connected to the input of latch 3 of the zero level, as well as to the control buses of the multiplexer 4 and demultiplexer 7. The bus of the higher ones -1 bits of the counter 2 is connected to one of the input buses of the adder 6, to the other input bus of which the output inverse bus of the multiplexer 4 is connected. The output bus of the adder 6 is connected to the address bus of the RAM 5. The output of the latter is connected to the information bus Discount entry demultiplexer 7, to each of whose outputs is connected driver 8 outputs pulses. The delayed pulses are sent to the information input 9 of the RAM 5. The sources of the delay codes of each channel are connected to the corresponding information bus of the multiplexer 4.

The multichannel generator is delayed. mmy pulses works as follows.

Counter 2 with its younger t-bits forms a cycle of alternate polling of delay codes, and the older 1-bits form the base address of RAM 5. The cycle begins by zeroing the younger bits and increasing the number written in the older ones, i.e. changing the base address by one, while the multiplexer. logical O in all bits, as a result, the address input of RAM 5 passes without changing

0 base address of this cycle Ap. If at this time a delayed pulse arrives at the information input D of RAM 5, a logical 1 is written to the cell at this address, if

5 there is no pulse, then O is written into it, since the logic level input is supplied with a low logic level from the output of the zero-latching circuit. Over the next

0; the RAM cycle cycles 5 are switched to read mode, and the inverted channel delay codes are received alternately on the accumulator bus. 6 and the T numbers or

5 relative address (relative to the base), equal to T |, k 1, ..., 2 - 1. The meaning of such a circuit in that (Fig. 2a) is that the base address moves in the field of cells

0 RAM 5, made activation of one of them at the time of arrival of the delayed pulse, and information is read from it after the time for which the pulse in this channel

j. is delayed. The delayed pulse from the output of the RAM 5 passes to the output of the demultiplexer 7, corresponding to the channel number defined in this cycle, since to the address

0 the input of the demultiplexer 7 receives the same code as that at the address input of the multiplexer 4. As a result of the time separation, the output pulses can be very short, therefore 5 O are received after distribution to the inputs of the formers 8 output pulses.

In order to avoid disruption of the generator due to the finite number of

Q cells of RAM 5, it is necessary to select the corresponding width of counter 2 and RAM 5 so that the update of information in this cell can occur only after reading the previous information, i.e. it is necessary that condition 7 e fTvo-x g, k be satisfied

In this case, the situation arises

as a result of modulo

two (i.e., without transferring from the senior bit of the adder (FIG. 26), does not cause a failure, since the cell with the base address A s is again polled after this time, since cell 0 is selected after cell 2 -1). depends on the duration of the delay t in the channel and its accuracy

installation E and is determined by the ratio / j / 1

With a T log, -g operation, take the nearest larger integer. The width of the adder b and the RAM 5 1 max ClogjT, if the number of channels n is set, then the bit is selected from the condition m Clogjn, then the counter size of the counter 2 is 1 + t. The frequency of the oscillator 1 of the reference frequency is determined from the condition

 G E.

Claims (1)

Invention Formula The multichannel generator of delayed pulses, containing a generator of the reference frequency, a counter, is connected to the output bus of the lower bits of which a latch of the zero level is connected,: a memory device and 7; "7-L7- / yr to output pulse drivers according to the number of delay channels, characterized in that, in order to extend the functionality by the possibility of delaying a series of pulses and simplifying the device, an adder, multiplexer and demultiplexer are inserted into it, and the memory 0 the device is made in the form of a random access memory, whose sampling input is connected to a reference frequency generator, and an output is connected to the address input 5 of the multiplexer through the adder, to the second input of which the output of the higher bits of the counter is connected, and the output of the lower bits of the counter is connected to the control input of the multiplexer and the demultiplexer, the output of the zero-level latch is connected to the recording enable input of the random access memory whose information input is connected to 5 bus input pulses, and the output is connected to the information input of the demultiplexer, the outputs of which are connected to the drivers of the output pulses, while the corresponding 0 The information bus of the multiplexer is connected to the bus of the delay code of each channel. (rig 2 Jl w 1IM2 Editor Y. Shulla Compiled by E.Surov Tehred I.Popovich, Proofreader A, Tsko Order 5127/51. Circulation 899 Subscription VNIIPI USSR State Committee . for inventions and discoveries 113035, Moscow, Zh-35, Raushsk na.b., d. 4/5 Production and printing company, Uzhgorod, ul. Project, 4 hh ) - Fig.Z