SU1244670A1 - Interface for linking electronic computer with communication channels - Google Patents

Abstract

The invention relates to the field of sophisticated technology and can be used in telecommunication systems. The aim of the invention is to reduce the conversion time of the information contained in the buffer memory. The device contains a switching node, a code converter, a buffer memory, a channel switching control node, a counter, a pulse distributor, a memory switch, the first, second, third triggers, the control register, the first, the second, the third And elements and the delay element. A device in one session provides for receiving or transmitting all information to communication channels. 1 il. to 4: 4 O)

Description

The invention relates to computing technology and can be used in telecommunication systems.

The aim of the invention is to reduce the transmission time of information.

The drawing shows a block diagram of the device.

The device contains a switching node 1, a parallel-serial converter 2 and a parallel, a buffer memory 3, a channel switching control node 4, a counter 5, a distributor 6 pulses, a memory switch 7, the first trigger 8, the second trigger 9, control register 10, first AND-11 element, OR element 12, third trigger 13, second And 14 element, third element. And 15, a delay element 16, transmitting and receiving input and output 17 of communication channels, information input and output 18 of the computer, output 19 of the transmission permission of the computer, output of the 20 clock frequency of the computer, output 21 of the computer starting . Exit 23 computer page selection.

The device works as follows.

The control register 10 is subdivided into parts, each of which corresponds to a certain communication channel number, and each positional position is a page in the buffer memory 3. All bits of the register 10 with the help of the distributor 6 pulses are successively polled according to with their priorities and in the order of their numbering. When recording information. In the exchange mode, register 10 records a code corresponding to the exchange mode. If, for example, in buffer memory 3 there are K. pages for A / communication channels, then the volume of register 10 in the exchange mode must contain iC A / bits, and each l / - part of it is allocated by node 1, as belonging to to the exchange mode in only one channel; In one communication channel, information is read from all sides of the buffer memory to which the units in register 10 corresponded. A page of a buffer memory is connected through a switch 7. A message is converted by a converter 2 according to clock pulses.

In the information exchange mode, the device access signal is sent to

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trigger 9. A clock pulse through elements 11 and 15 is applied to the distributor 6 pulses and polls the first bit of register 10. If O is recorded in this register bit, the state of the device elements does not change and the next clock pulse is sent to the polling of the next bit Yes, register 10, if 1 is recorded, the signal from register 10 is fed to the decoder 7 to connect the corresponding page of the buffer array and, via the OR 12 element, switch trigger 13 to zero zero. The next clock pulses through the delay element 16 and the AND 14 element arrive at counter 5. From the first counter output, signals are sent to the input of converter 2. After the conversion of the message from the second output of counter 5 is completed, a signal is output, which through the OR 12 element. trigger 13 in one state.

Circuit AND 14 opens, and the clock pulses are again received through - the distributor 6 pulses to poll register 10. In this way, the entire register 10 is sequentially polled and information is read into each channel from the specified buffer pages. In the information receiving mode, trigger B operates, which, through node 4, connects the communication channel | 1Y to converter 2; Information is also recorded in the buffer section 1 in accordance with the information in register 10 about the exchange mode. In this case, each register bit register 10 must be written,

Upon the completion of the reception or transmission of information on the output of the pulse distributor, a signal is taken which arrives at the trigger 9 and brings it to the zero state. In this case, the Ready signal is generated at output 22. Thus, when a device is accessed, all control bits are polled by clock pulses, and if O is read from the control register, then the next poll is the next clock pulse, if 1 is a clock, the interrogation signal is generated in a time interval equal to convert page. This leads to a decrease in the time of transformation of information in the buffer memory.

Claims (1)

Invention Formula A device for interfacing an electronic computer with communication channels, comprising a switching node, a serial-to-parallel converter and a backward buffer memory, a decoder, a channel switching control node, a control register, the first, second triggers, the first element is And, with 10 the first information input and output of the evil switching are connected respectively with the transmitting and receiving communication channels, the second information input and output of the switching node are connected with 15 respectively with the first information The output and input of the serial code converter to parallel and vice versa, the second information input and output of which are connected respectively to the first information output and input, the buffer memory, the second information input and output of which are connected respectively to the information output and input 25 of an electronic computer (computer), the channel select input of the switching node is connected to the output of the channel switching control node, the reception enable input and the channel selection input of which are connected respectively to Exit first flip-flop and a control register, and An information input of which counter, the first trigger input connected respectively to the outputs of the address computer and receiving authorization, the control register output is connected to an input of the address decoder, the output of which is connected to the address input 35 s 0 5 0 5 o . the buffer memory, the single input of the second trigger is connected to the start output of the computer, the single and zero outputs of the second trigger are connected respectively to the first input of the first element And and to the alarm input of the computer mode, the second input of the first element And is connected to the clock output of the computer, characterized by that, in order to reduce the information transfer time, an OR element, a second, a third AND element, a third trigger, a counter, 3S} are introduced into it, a delay distributor, a pulse distributor, and the output of the control register is connected to the first element OR, the second input and output of which are connected respectively to the information output of the counter and the counting input of the third trigger, the unit and zero outputs of which are connected to the first inputs of the second and third elements respectively, the second inputs of which are connected respectively to the output of the delay element and to the code the first element And, the outputs of the second and third elements And are connected respectively to the counting input of the counter and the input of the pulse distributor, the first and second outputs of which are connected respectively Effectively to the synchronization input of the control register and to the zero input of the second trigger, the output of the first element I is connected to the input of the delay element, the transfer output of the counter is connected to the enable input of the serial to parallel converter and vice versa. Editor M. Tsitkina Compiled by S. Buruhin. Tehred M. Khodanich Proofreader S. Shekmar Order 3919/52 Circulation 671 Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhgorod, Projecto st., 4