SU1332325A1 - Device for mating a computer with users - Google Patents

Abstract

The invention relates to computing and can be used for communicating microcomputers with external D g devices, as well as for interconnecting two computers. The aim of the invention is to reduce the data transmission time from the computer to the subscriber. The device comprises a transmission-reception unit 1, the second element OR 2, the block 3 of permanent memory, register 4, the first, second, third elements AND 5-7, the element NOT 8, the first element OR 9, the first group of 10 elements AND, a second group 11 of elements AND, a state register 12, a group of 13 communication units with a subscriber. The device reduces the time of information transfer between the computer and the subscriber due to greater automation of the process of receiving and transmitting information, i.e. The device takes over a number of computer exchange functions. 1 hp f-ly, 2 nl. I (L

Description

The invention relates to computing and can use pflu microcomputer communication with external devices (display, digital print, perforator, etc.) as well as to connect two microcomputers.

The purpose of the invention is to reduce the time of data transmission from a computer to a subscriber.

Figure 1 presents the block diagram of the device; Fig. 2 is a diagram of a group of communication units with a subscriber.

The device (figure 1) contains block 1

ten

The number of which is equal to the size of the address space of the computer. For each of these addresses, in block 3, a binary code is recorded, with a size (), where n is the number of information channels (IR) of the subscriber with which the computer is connected. The signals from the outputs of block 3 are fed to the inputs of register 4 and are fixed in it by the arrival of the address strobe to the input 17. The code from the output of register A is controlling to generate signals: recording information on inputs 21 in n blocks 13, recording information on

reception-transmission, the second element OR 2, 15 input 23 into state register 12 (PC), permanent memory unit 3, register 4, read information at inputs 22

the first, second, third elements are NOT 8, the first element is OR 9, the first group is 10 AND elements, the second group is 1I AND elements, state register 12, and 13 communication blocks with the subscriber.

The device also has an internal data bus 14, data input / output 15, address input 16, address synchronization input 17, data output input 18, data input input 19, initial installation input 20, write inputs 21 and read unit 22, inputs 23 read and 24 write to the register 12, the inputs 25 of the reading strobe and the inputs-outputs 26 of the data of the group 13 of the communication unit with the subscriber, the output 27 and the input 28 of the input (the input 29 of the control of the receiving and receiving unit 1. Each communication unit with subscriber group 13 contains (2) block 30 registers, block 31 receivers, the element is NOT 32.

The unit of reception and transmission can be performed, for example, on m / s type K500 BA86 or K589AP16.

When exchanging information with the subscriber, the computer must perform the following actions: reading the input acknowledgment signals 28 through register 12, analyzing these signals, writing information to blocks 13, reading information from blocks 13, writing the output acknowledgment signals 27 to state register 12. For the subscriber exchange is as follows: analysis of the output acknowledgment signals 27; recording information in blocks 13 or reading from blocks 13; issuing input acknowledgment signals 28.

The device works as follows.

The exchange between the computer and the subscriber begins with the arrival of the address from the E VM, once

The number of which is equal to the size of the address space of the computer. For each of these addresses, in block 3, a binary code is recorded, with a size (), where n is the number of information channels (IR) of the subscriber with which the computer is connected. The signals from the outputs of block 3 are fed to the inputs of register 4 and are fixed in it by the arrival of the address strobe to the input 17. The code from the output of register A is controlling to generate signals: recording information on inputs 21 in n blocks 13, recording information on

0

0

five

units 13 read information at input 24 of PC 12 by the arrival of a signal at input 18 of the device, if in the corresponding bits at the output of register 4 is written 1. When l is in (n +2) -th bit at the output of register 4 and the presence of signal at input 18 is generated at the input 23 of the recording signal 5 in the PC 12.

If there is 1 in (n + 2) -th bit and there is a signal at input 19 (input gate), a read signal at input 24 of PC 12 is generated and information from PC 12 is fed to the internal data bus.

In the presence of O in (n + 2) -th bit, the signals at the inputs of the read 24 and write 23 are not processed. Thus, the device allows accessing the PC 12 at a fixed address on the computer bus bar by writing to the (n + 2) -th bit of block 3 at the given address 1. If there is 1 in (n + 1) -th bit, Q of the incoming signal at input 19 and occurrence 1 at the nth output of register 4 at the output of the nth element I 11 produces a signal to read information at the input 22 of the nth block 13. When this signal is received, the information from the nth IR 26 via block 13 enters the bus 14. Thus, the device allows you to read information in the Input cycle from the nth block 13 at a fixed address on the computer bus . At this address in block 3, 1 should be written in the nth digit, where n is the number of the block from which information is read, and 1 in (n + 1) th time.

When the p-th signal appears at the input 22 of the information reading from block 13, or the read signal from the input 24 of PC 12 at the output of the element OR 2

five

0

A transmission control signal appears at input 29, switching unit 1 to transfer information to a computer; in all other cases, unit 1 is switched to transmitting information from a computer,

If there is a C (1 + 1) th bit and there is a signal at input 19, or regardless of the (C + 1) th digit and a signal at input 18, as well as with one or more p – x the outputs of register 4, the outputs of elements AND of the first group 10 produce signals for recording information at inputs 21 into 5th blocks 13. Such an organization makes it possible to generate recording signals when outputting information at fixed addresses on a computer bus. When recording in the nth digit in block 3 1, the nth signal to write information to block 13 at input 21 is generated. It is possible to write the same information simultaneously to blocks 13, which is necessary at this address to the corresponding -e block 3 bits to add l, i.e. in this case, the device saves the (n-1) transfer command.

The device also makes it possible to generate recording signals at inputs 21 when accessing any address in the address space of a computer (for example, computer memory locations), if I recorded at this address in the corresponding nth bits, i. performs parallel loading of information into one or several blocks 13 when entering or outputting to a cell with an address from the address space of a computer, thus saving one or n forwarding commands, respectively.

Reset the device occurs on a signal to the input 20 of the initial installation.

Blocks 15 operate as follows: when a recording signal appears at inputs 21, data from bus 14 is written into the internal register of the block, from which information is output to IR 26 by a read signal at input 25. Information is transmitted from IR 26 to bus 14 by a signal 22 inlet readout.

PC 12 operates in two modes: software and interrupt. Both in this and in the other mode, upon the arrival of a readout signal at input 24, the acknowledgment signals 28 are read into the internal bus 14 via the state register buffer. According to

0

five

0

five

0

five

0

five

0

five

The arrival of the write signal to the input 23 of the information from the bus 14 is written to the register and outputted by the acknowledgment signals from the inputs 27. In the interrupt mode, the acknowledgment signals at the inputs 27 are used as interrupt request signals, which are reset upon the arrival of signals at the inputs 28.

Claims (2)

1. A device for interfacing a computer with subscribers, comprising a receiving-transmitting unit, a group of communication units with a subscriber, first inputs / outputs of data of communication units with a subscriber are connected via data to the first input output of the receiving and receiving unit, the second input output which is connected to the input-output of the device to connect to the input-output data of the computer, the second inputs-outputs of the data blocks of communication with the subscriber are connected to the input-output of the device for connection to the inputs-outputs of the data of the respective subscribers, reduce and the time of data transmission from the computer to the subscriber, a block of permanent memory, a register, first to third elements AND, an element NOT, first, second elements OR, a status register, first and second groups of elements AND, the address input the fixed memory unit is connected to the input of the device for connecting to the address output of the computer, the output of the permanent memory unit is connected to the information input of the register, the i-th (i 1, n) output of the register (where n is the number of subscriber channels) is connected to the first inputs ix of elements I of the first, second groups, (n + 1) -th output reg the country is connected to the second inputs of all elements of the second group and to the input of the element NOT, (n + 2) -th register output is connected to the first inputs of the first, second elements AND, the register synchronization input is connected to the device input for connecting to the synchronization output of the computer , the second input of the second element I is connected to the input of the device for connecting the input data of the computer to the output with the first input of the third element I. and the third inputs of the elements II of the second group, the second input of the first element I connected to the first input of the first el OR and with the input of the device for connecting the output of the computer data to the output gate, the output of the element is NOT connected to the second input of the third AND element, the output of which is connected to the second input of the first OR element, the output of which is connected to the second inputs of the AND elements of the first group, the register reset inputs and the status register is connected to the input of the device for connecting to the output of the initial installation of a computer the output of the first element I is connected to the input gate of the state register, the input of the reading gate of which is connected to the first input m of the second element OR and with the output of the second element AND, the input-output of the data of the status register is connected to the first input-output of the data of the receiving-transmitting unit, the output of the i-element of the AND group of the first group is connected to the input of the recording strobe of the i-ro communication with the subscriber of the group, the output of the i-ro element And the second group is connected to the first input of the strobe of the reading of the i-ro communication unit with the subscriber of the group and with the iM input (i 2, n + 1) of the second element OR, the output of which is connected to the input choice of direction the transmission of the reception-transmission block, the output of the status register is connected to the output of the device for connecting the subscriber's acknowledgment input, the information INPUT of the status register is connected to the input of the device for connecting the subscriber's confirmation output, the second inputs of the strobe of the communication blocks with the subscriber of the group are connected to the device input for connection to the subscriber's information output. 2. POP.1 device, characterized in that each group communication unit contains a register block, a receiver block and an NOT element, the first input / output of the data of the block is connected to the information input of the register block and to the output of the receiver block, the second input-output the data block is connected to the output of the register block and to the information input of the receiver block, the resolution input of which is connected to the read input, the write record of the block is NOT connected to the synchronization input of the register block, the input strobe of the block is connected to the enable input b lock registers. Editor E. Papp Compiled by S. Buruhin Tehred L. Serdyukova 3834/45 Circulation 672 Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhgorod, st. Project, 4 2 Proofreader I. Muska