SU1262509A1 - Device for linking computer interfaces and external storage - Google Patents

Abstract

The invention relates to computing and is intended for interfacing a software-controlled channel of a computer with external memory devices on magnetic disks. The aim of the invention is to reduce the data transmission time through the interfaces of the associated devices. The device contains a computer interface control register, a switching unit of control signals of a computer interface, a control word register, a first, second control signal registers, a data transmission control unit, a buffer storage unit, an external memory interface control switching unit, an interface control register , external memory, the first - the fifth group of elements AND, the first, second group of elements OR. The use of the device allows independent and simultaneous control of the computer I / O interface and external memory, which provides independent and simultaneous data transfer between the storage unit and interfaces of the interfaced devices (Devices with different data transfer rates 5 or less.

Description

N3

05

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SP

The invention relates to computing and is intended for interfacing a software controlled computer channel with external memory devices on magnetic disks.

The aim of the invention is to reduce the data transmission time through the interfaces of the associated devices.

FIG. 1 shows a block diagram of the device; in fig. 2 is a diagram of a data transmission control unit; FIG. 3 - functional diagram of the switching unit of control signals of the computer interface; in fig. 4 is a functional diagram of the switching unit of control signals of the external memory interface; in fig. 5 is a timing diagram of the operation of the data transmission control unit.

The device contains output 1 of computer data, computer interface control register 2, first group 3 of elements I, computer control switching unit 4 of control interface of computer, register 5 of control word, first register 6 of control signals, second group of 7 elements I, second register 8 control signals, data transmission control unit 9, the second group of 10 OR elements, the first group of 11 OR elements, the buffer storage unit 12, the fourth group of 13 AND elements, the fifth group of 14 AND elements, the third group of AND elements, 16 switching unit control signals external interface memory catch, external memory interface control register 17, external memory data input 18.

The data transmission control unit contains the first element AND 19, the second delay element 20, the first element OR 21, the first counter 22, the fourth element OR 23, the second element AND 24, the second element OR 25, the third 26 and the second 27 triggers, the comparison circuit 28, The group of 29 elements is And, the third element is And 30, the third is a group of 31 OR elements, the first delay element 32, the second counter 33, the seventh 34 and fifth 35 And elements, the third element OR 36, the third delay element 37, the seventh group 38 And elements , the sixth 39 and the fourth 40 elements And, the seventh 41, the fifth 42 and sixth 43 elements LEE, the first 44 and fourth 45 triggers. In addition, in FIG. 2 designates the first control input 46, the output 47 of the seventh OR element, the single output 48 of the first trigger, the output 49 of the first delay element, the output 50 of the fourth trigger, the data identification input 51, the outputs 52 of the first OR element, the output 53 of the third trigger, output 54 the second delay element, the single output 55 of the second trigger, the second control input 56, the output resolution 57, the address output 58, the first and second gate outputs 59 and 60 of the data transmission control unit.

The switching unit of the control signals of the computer interface contains the first 61, second 62, third 63, fourth 64 and fifth 65 elements NOT, control 66, sets the data exchange protocol 67 and resets 68 inputs, as well as the outputs of the interface control switching unit 4 Request computer 69, state vector 70, data reception permission 71 and control sector formation 72, AND-OR matrix 73, delay element 74, trigger 75, first 76 and second 77 And elements, first 78 and second 79 OR elements, register 80 switching unit control signals of the computer interface.

Control switching unit

the external memory interface contains the matrix 81 of the AND-OR elements, the I / O control inputs 82, the resolution input 83, the input 84 of the communication protocol setting,

control vector generation output 85, state vector output 86, HE 87-91 first-fifth elements, register 92, first and second elements OR 93 and 94.

In addition, in FIG. I depicted the entrance

95 device reset, computer control input 96, computer I / O resolution output 97, computer data input 98, external memory control output 99, external memory control input 100, and external memory data output 101.

The initialization of the device (Fig. 1 and 2).

For resetting, a "STAT. As a result, counters 22 and

5 33 are cleaned. The specified signal sets to zero through the OR element 23 trigger 26, through the OR element 25 trigger 27, through the OR element 36 trigger 44, through the OR element 43 trigger 45. In the initial state, the AND 19 element is connected to one of the inputs the zero output of flip-flop 44 is allowed and is in the wait state of the control signal from the output of block 4, and the AND 24 element through one of the inputs connected to the single output of the flip-flop 44 is prohibited. Element 39 and one of the inputs connected to the zero output of the trigger 26 is allowed and is in the wait state of the control signal from block 16, and element 40 through one of the inputs connected to the single high code of the trigger 26 is prohibited. Elements 30 and 35 on one of the inputs connected to the sensor outputs of the flip-flops 27 and 44, respectively, are prohibited. Signals and information from the outputs of block 9 are not

5 are supplied, as a result of which the groups of elements AND 7 and 13 are prohibited by the corresponding inputs, and information is not received in block 12.

Data transfer from external memory to computer

1. Inputting control information into the device and initiating the data exchange procedure (Figs. 1 and 2).

From the computer channel, the control information on the data bus 1 goes to one of the inputs of the group of elements I 3, and the control signals (control field) to one of the inputs of block 4, as a result of which the output of block 4 generates a signal allowing another input a group of elements AND 3. From the output of a group of elements AND 3, the control information enters register 5, where it is stored until the end of the exchange. Omitting the transfer procedures between the computer and the external memory of the control and diagnostic information, we will consider directly the procedure for transferring data between the computer and the external memory.

Under the action of the control information of register 5, blocks 4 and 16 begin simultaneously the processing of data exchange protocols over computer input-output interfaces and external memory. At the same time, the control vector for the computer I / O interface is formed on register 2 by the action of signals arriving at its input from one of the outputs of block 4, and the vector control interface of the external memory is formed at register 17 by the action of signals arriving at its input from one from the outputs of block 16. The states of registers 2 and 17 are transmitted to the control buses of the computer interfaces and external memory, respectively.

2. Transfer of data from external memory to block 12 (Fig. 1, 2, 5a).

This procedure involves the formation of the addresses of the cells of block 12 and the recording at these addresses of information from the external memory.

2.1. Formation of the address of the cell in block 12.

Data from the external memory via the data bus 93 arrives at one of the inputs of the group of elements And 13. At this moment, the data transfer is identified via the external memory control bus 91. The control information is fed to one of the inputs of block 16, and the latter generates a control request signal (Fig. 5, pos. 46), which in the counter 33 forms the address of the data record in block 12. The address information is sent to Vta one and the inputs element groups and 38.

2.2. Control of operation of block 12 in the mode of operation “Record.

When performing a write operation of data coming from an external memory, the device operates as follows.

The request signal (Fig. 5, pos. 46) is fed to one of the inputs of the And 39 element, the other input of which is allowed by the zero output state of the trigger 26, and to one of the inputs of the And 40 element that is prohibited by the other input by the state of the single output of the trigger 26 The output signal of the element And 39 through the element OR 41 (Fig. 5, pos. 47)

sets the trigger 44 to the one state and enters the input of the delay element 32, the output of which (Fig. 5, pos. 49) sends a signal through the OR 36 element to the trigger 44 to the initial zero state. As a result, on trigger 44 on impulse

the strobe is formed (Fig. 5, pos. 48), the duration of which corresponds to the cycle duration of the buffer memory 12. This strobe allows a group of elements AND 38 to enter through another input, the information from which through the group of elements OR 31 comes as the address of the data word to the address input of block 12. The same strobe, being one of the output signals of block 9, permits another group of elements And 13, as a result of which the data word from the external memory through groups 13 and 11 elements enters the information input of block 12.

The control signals from the output of block 16 are set one by one.

from the bits of the second register of control signals 8, the state vector of which, if there is a signal from the output of the block 9 arriving at another input, through the group of 10 elements OR controls the operation mode of the block 12 (in this case the operation Record ). As a result, the data word received from the external memory is written to the block 12 at the address generated at the counter 33. The writing of the next data word is carried out similarly to the one considered.

3. Data transfer from block 12 to the computer (Fig. 1, 2, 5 b).

Simultaneously with writing the data words from the external memory to the block 12, the written data is read (sampled).

from block 12 and sending them to the computer. The reading procedure includes the formation of the addresses of the cells of block 12 and the reading of information at these addresses information data with the subsequent transfer them to the computer.

3.1. The formation of the address of the cell block 12

When determining the address of the cell in block 12, the device operates as follows.

Unit 4, controlled by a register 2 by a computer input-output interface, generates a request signal (FIG. 5, pos. 51), which is fed to the counting input of counter 22, where the address of the data word is received to one of the inputs of the AND 29 group of elements.

3.2. Control of operation of unit 12 in the operation mode “Reading.

The request signal (Fig. 5, pos. 51) is fed to one of the inputs of the element And 19,

the other input is allowed at this moment by the state of zero output of the trigger 44 and to one of the inputs of the AND 24 element, the other input of which is at this moment prohibited by the state of the single output of the trigger 44. The output signal of the AND 19 element through the OR 21 element (Fig. 5, position 52) sets the trigger 26 to one state and enters the input of delay element 20, the output of which (Fig. 5, position 54) transmits the signal through the OR element 23 to the trigger 26 to the initial zero state. As a result, on the trigger 26 to a strobe signal is generated to the request signal (Fig. 5, pos. 53), the duration The duration of which corresponds to the cycle time of the buffer memory 12. The gate formed on the trigger 26 allows the group of 29 AND elements to another input, the information from the output of which through the group of logical elements 31 OR, as the address, fetches the data word to the address input of the block 12. The same gate , Being one of the output signals of block 9, enables one of the inputs to a group of 15 elements I. The control signals from the output of block 4 establish, using one of the inputs, the bit of the first register 6 of the control signals the rest of which, in the presence of the output signal of block 9, arriving at its other input, through a group of 10 elements OR controls the mode of operation of block 12 (in this case, the reading is performed).

As a result, the information read from block 12 goes to another input of the group 15 of elements I, from the output of which this information goes to the input 98 of computer data

Since the data transfer rate through the computer I / O interface is lower than the data transfer rate through the external memory interface, provided that the data array is simultaneously written to the block 12 from the external memory and the data array is read from the block 12 to the computer, the entire data array will be transmitted without distortion.

Data transfer from a computer to an external memory (Fig. 1, 2, 5 a, b).

In contrast to the considered mode, when transferring data from a computer to an external memory, the control signals of block 4 set the bits of register 6 so that its state vector through a group of 10 elements OR provides the write mode of the spruce data into block 12. At the same time, the data information into block 12 from a computer through a group of 7 AND elements permitted by a single state of trigger 26, and a group of 11 OR elements (Fig. 56).

The control signals of block 16 set the bits of register 8 in such a way that its state vector provides a mode of reading information from block 12, which is fed to one of the inputs of a group of 14 AND elements, the other input of which is allowed at this time by the state of a single trigger output 44. As a result, information from the output of a group of 14 elements And goes to the data bus of external memory (Fig. 5a).

Since the recording of information from the computer in block 12 is carried out at a speed lower than the reading from block 12 to the external memory, the initiation of the reading procedure with respect to the writing procedure is delayed by a fixed time interval, which is determined based on the difference in data transmission speeds . Information about this difference is transferred to register 5 in the initial phase of the exchange, where it is stored during the entire exchange time.

The output of register 5, corresponding to the bits where this information is stored, for testing the required delay is connected to one of the inputs of the comparison circuit 28, the second input of which receives information from the output of the counter 22. When transmitting information from the computer to the block 12, the counter 22 generates the address block 12, calculates the number of data words transferred to the block 12, which determines the time interval of the delay. When the state value reaches the counter 22 corresponding to the specified time interval, the output of the circuit 28 is a signal that enters the block 16 and allows it to operate in accordance with the mode of reading information from block 12 and transmitting it to the external memory. Subsequently, the operation of "Writing information from a computer to block 12 and" Reading information from block 12 to an external memory can be performed simultaneously, depending on the moment the reading operation arrives to the external memory. At that, the worked out time interval ensures the end of reading the last word of the information array from block 12 and its transfer to the external memory not earlier than the end of writing this word from channel 1 of the computer to block 12, which is a necessary condition for the reliability of information transfer.

Conflict resolution

1. The request from the computer comes when the exchange cycle between the external memory and block 12 is not completed (Fig. 2, 5 c).

In this case, when a request signal from a computer (Fig. 5, pos. 51) arrives at one of the inputs of the logic element AND 19, the latter remains closed at the other input by the zero output of the trigger 44, as a result of which the output signal of the And 19 is not is. The request signal (Fig. 5, pos. 51) also goes to one of the inputs of AND 24, the other input which is allowed at this moment by the single output of trigger 44. The output signal of AND 24 sets the trigger 27 to the single state ( Fig. 5, pos. 55), thereby remembering the request from the side of the computer channel that was not serviced. At the end of the data word transfer cycle from the external memory, the output signal of the delay element 32 (Fig. 5, pos. 49 is fed to one of the inputs of the And 30 element, which is enabled by the other input by the state of a single output of the trigger 27. The output signal of the And 30 element through the OR 21 element (Fig. 5, pos. 52) sets the trigger 26 into one state (Fig. 5, pos. 53) and starts the cycle of data exchange between the computer and block 12. The signal from the output of the AND 30 element through the OR 25 element sets trigger 27 to the initial zero state.

2. The request from the external memory arrives when the cycle of exchange between the computer and unit 12 is not completed (Fig. 2, 5 g).

In contrast to the considered, the request for external memory is remembered on the trigger 45, since the request signal (Fig. 5, pos. 46) arrives at one of the inputs of the And 39 element via the second input, which at this moment is forbidden by the zero output of the trigger 26, and one of the inputs of the element 40, another input which is at this moment allowed by the state of a single output of the trigger 26. The output signal of the element 40 through the element OR 42 sets the trigger 45 (Fig. 5, pos. 50) to the state 1. As a result, the request to exchange the data word from the external memory is stored on the trigger 45 and is stored until the end of the data exchange cycle between the computer and the block 12. At the end of this cycle, a signal appears at the output of the delay element 20 (Fig. 5, pos. 54) ) which is fed to one of the inputs of AND 35, the other input which is allowed at this moment by the state of a single output of the trigger 45 (an unserved request is stored from the external memory). The output signal of the element 35 through the element OR 41 sets the trigger 44 to the one state (Fig. 5, pos. 48), and through the element OR 43 - the trigger 45 to the initial zero state (Fig. 5, pos. 50). From this moment on, the cycle of exchanging the data word between the external memory and the block 12

3. Requests from the computer and external memory arrive when the exchange cycles from the external memory and computer, respectively, are not completed (Fig. 2, 5 ().

This situation is a superposition of considered situations 1 and 2 and is fully described in the descriptions provided for them.

4. Requests from the computer and external memory are received simultaneously (Fig. 2, 5 e).

With simultaneous requests from a computer (Fig. 5, pos. 51) and external memory (Fig. 5, pos. 46), the triggers 44 and 26 are set to one state (Fig. 5, pos. 53, 48), the state of the triggers 27 and 45 is undefined. The analysis of such a situation and bringing the device into a regular state with the subsequent processing of incoming requests is carried out as follows. The states of the single outputs of the flip-flops 26 and 44 allow, on both inputs, an AND 34 element, the output of which, through the delay element 37, sets the device triggers to the state corresponding to the maintenance request

side of the computer and memorizing the request from the external memory with its subsequent maintenance.

The delay element 37 serves to generate a control signal at the end of

transients switching triggers 27 and 45, caused by the simultaneous appearance of request signals from the computer and external memory. The output signal of the delay element 37 through the logical element OR 36 transfers the trigger 44 to the initial zero state (Fig. 5, pos. 48) through the OR element 42 translates (or confirms) the trigger 45 into the single state (Fig. 5, pos. 50 ) and through the element OR 25 translates (or confirms) the trigger

27 to the initial zero state (Fig. 5, pos. 55).

From this moment, the servicing of the request received from the computer begins, and the request from the external memory is stored in

trigger 45 (Fig. 5, pos. 50). At the end of the data word exchange cycle between the block 12 and the computer, a signal appears at the output of the delay element 20 (Fig. 5, pos. 54), which is fed to one of the inputs of AND 35, the other input of which is at this moment allowed by the unit state trigger output 45. The output signal of the element 35 through the element OR 41 sets the trigger 44 to one (Fig. 5, pos. 48), and the trigger 45 through

the OR 43 element returns to the initial zero state (Fig. 5, pos. 50). At this moment, the cycle of exchanging the data word between the external memory and the block 12 is fulfilled.

Claims (1)

Thus, the use of the device allows for independent and simultaneous control of the computer I / O interfaces and external memory, which provides independent and simultaneous data transfer between the block 12 and interfaces of the interfaced devices having different data transfer rates. An apparatus for interface of computer interfaces and external memory, comprising a switching unit of control signals of a computer interface, a buffer storage unit, a control word register and a first group of elements AND, the information input of the switching unit of control signals of a computer interface is connected to an information output the control word register, the input connected through the elements of the first group to the output of computer data, characterized in that, in order to reduce the time of data transmission through the interfaces of the computer devices, an external memory interface control signal switching unit, a data transmission control unit, a computer interface control register, the first and second control signal registers, the first and second groups of OR elements, the second five groups of AND elements, the control register external memory interface, where the output of the computer I / O resolution is connected to the control input of the switching unit of the control signals of the computer interface, the first inputs of the elements AND of the second and third groups and the control input of the first register and the control signals are connected to the first gate output of the data transmission control unit, the second gate output of which is connected to the first inputs of elements of the fourth and fifth groups and to the recording input of the second register of control signals, control inputs and data and control outputs and external external memory these are connected respectively to the output of the external memory interface control register, to the outputs of the elements of the fifth group, to the first information input of the switching unit of the control signals of the external interface interface The second information input, the control input, the first, second and third outputs of the switching unit of the external memory interface signal are connected respectively to the first bit output of the control word register, to the readout output of the control unit data transmission, with the information input of the external memory interface control register, with the information input of the second control signal register, with the first control input of the data transmission control unit, input id Data identification and the second control input of which are connected respectively with the first output of the switching unit of the control signals of the computer interface and the second bit output of the control word register, the outputs of the first and second registers of the control signals are connected respectively with the first and second inputs of the OR elements of the second group The outputs of which are connected to the inputs of the mode of the buffer storage unit, the inputs of the address and data of which are connected respectively to the address output of the data transmission control unit and from elements of the first group, the first, second inputs of which are connected respectively to the outputs of elements of the fourth group and the outputs of elements of the second group, the second inputs of which are connected to the output of computer data, the output of the state vector, the second and third outputs of the switching control signals the computer interface is connected respectively to the information input of the first control signal register, to the second inputs of the AND elements of the first group and to the information input of the computer interface control register, the output of which is is connected with the control input of the computer, the information input of the computer is connected to the outputs of elements of the third group, the second inputs of which are connected to the information output of the buffer storage unit, the reset input of the device is connected to the reset inputs of the data transmission control unit 4 of the control signals of the interface of the computer interface the data transmission control unit contains the first and second counters, the first - the fourth triggers, the first - the seventh elements AND, the first - the seventh elements OR, the first - the third delay elements, the first and And a group of elements AND, a group of elements OR, and the data identification input of the data transmission control unit is connected to the counting input of the first counter and the first inputs of the first and second elements AND, the output of the first element AND is connected to the first input of the first OR element, the second input of which is connected to the output The third element And with the first input of the second element OR, the reset input of the data transmission control unit is connected to the reset inputs of the first and second counters, with the first inputs of the third, fourth and sixth elements OR and the second input of the second element OR, the outputs of the third, second, fourth and sixth elements OR are respectively connected to the reset inputs of the first, second, third and fourth triggers, the first control input of the data transmission control unit is connected to the counting input of the second counter and the first the inputs of the fourth and sixth elements And connected by the output with the first input of the seventh element OR, the second input of which is connected to the output of the fifth element And and the second input of the sixth element OR, the output of the seventh element OR connected to the installation input of the first trigger and to the input of the first delay element, the output of which is connected to the second inputs of the third OR element and the third AND element, the output of the first OR element is connected to the installation input of the third trigger and to the input of the second delay element, the output of which is connected to the second input the fourth OR element and the first input of the fifth AND element, the second input of which is connected to the output of the fourth trigger, the installation input of which is connected to the output of the fifth OR element, the first input of which It is connected with the output of the third delay element and with the third inputs of the second and third OR elements, the second input of the fifth OR element is connected to the output of the fourth AND element, the second input of which is connected to the first input of the seventh AND element, with a single output of the third trigger, with the first inputs of the Both the first group and the first gating output of the data transmission control unit, the second gating output of which is connected to the single output of the first trigger, with the first inputs of the output of the elements of the second group and the second the strokes of the second and seventh elements And, the output of which is connected to the input of the third delay element, the output of the second element And is connected to the installation input of the second trigger, the output of which is connected to the first input of the third element And, the output of the first counter is connected to the First input of the comparison circuit and the second inputs elements AND of the first group, the outputs of which are connected to the first inputs of the elements OR of the groups, the outputs of which are connected to the address output of the data transmission control unit, the output of the read resolution and the input of the state vector which is connected respectively to the output and to the second input of the comparison circuit, the output of the second counter is connected to the second inputs of the AND elements of the second group, the outputs of which are connected to the second inputs of the OR elements, the zero output of the third flip-flop is connected to the second input of the sixth element AND, the zero output of the first flip-flop connected to the second input of the first element I. cpus.1 68 Usto 60 59 80 Life style C6 6S 67 S9 70 IL 72 r i zg  W