SU1446625A1 - Device for interfacing electronic computer with subscriber - Google Patents

Abstract

The invention relates to the field of computer technology and can be used in computer complexes having a common bus interface. The aim of the invention is to improve performance by simultaneously writing arrays of information into several memory blocks of a subscriber at the same time. The device comprises a decoder 1, a control register 2, an interrupt block 3, a switch 4, a switch register 5, a sampling block 8, a mask register 9. The device provides parallel operation of the computer with several devices connected to the Common bus interface simultaneously with the programmed device addresses. 1 hp f-ly, 2 ill.

Description

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The invention relates to computing and can be used in computing complexes having a common bus interface.

The aim of the invention is to increase productivity by simultaneously writing arrays of information into several memory blocks of the subscriber at the same time,

Fig, 1 shows the block diagram of the device; in fig. 2 - block diagram, sampling.

The device (Fig. 1) includes a de-encoder I, a control register 2, an interrupt block 3, a switch 4, a switching register 5, a computer 6, a subscriber 7j a sampling block 8 and a mask register 9.

Sampling unit 8 contains (Fig. 2) element 10. comparison, element OR P block 12 elements AND, element AND 13 and Tpi-irrep 14.

The device is intended for matching n (compatible signals of two interfaces with the possibility of parallelizing synchronization signals on the perimeter subscriber trunk. Most of the common bus signals are interpreted into the corresponding peripheral trunk signals. An address zone is assigned to work with the peripheral devices of the computer memory ), the window size is selected when designing a specific

systems and may be 512, IK,

2k, 4k, 8k, 16k, 32k words. Several devices can be located on the periphery of the Eynya Railway. The addresses of the device registers are identical among themselves and stored in a window address address. Appeal to specific; devices of the peripheral system is provided by separating the signals of cgronization.

The device exchanges data between any preassigned peripheral devices and an operational computer under the control of a program using interrupts. In accordance with the program, the time / transmission of the data is determined and the first stage is initiated. At the first stage of the exchange, the control register 2 and the mask register 9 are programmed. The control register and mask register bits are determined by the number of subscriber units.

The interrupt resolution is entered into the control register, and the conditional register is entered into the mask register in the position code.

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subscriber peripheral numbers for which subsequent information is intended. There is a one-to-one correspondence between the bits of the mask register and the conventional numbers of the peripheral devices of the subscriber: the i-th bit of the mask register corresponds to the i-e peripheral device of the subscriber.

To program the device registers on the lines of the common bus ERM, the address of the corresponding register, the write code, and the data after a fixed delay are set. The address received from the computer 6 into the decoder 1 is decrypted, and a write signal is received from the clock signal and the corresponding register. After writing data to the register, the decoder 1 generates the response of the clock signal and sends it to the computer. The computer receives this clock signal, removes its synchronization signal, and then the data, the address, and the control signals. After the clock signal is removed, the device removes the response clock signal and the first stage of the device initialization is completed,

Then the computer starts the transfer of the array of information to the peripheral devices of the subscriber in accordance with the mask code.

For this computer puts on the line. shared bus address from the floor of the window address, the write code, the data and after the fad HpoBaHHii delay the sync signal. Decoder 1 determines that the address refers to the addresses of the peripheral system and sends a synchronization signal to sampling unit 8. The synchronization signal polls the block of 12 elements AND, the second inputs of which receive the mask code from the register 9. From the outputs of the block of 12 elements AND, the synchronous signals are output to the authorized subscriber devices. After the write operation is executed, the device sets asynchronously the clock signals and the response signals, which are respectively transmitted to the sampling unit 8 and to the control register 2. With the appearance of the first clock signal, the OR element 11 of the sampling block 8, which opens the AND 13 element and removes the reset signal from the trigger 14, with the arrival of the last clock signal, the comparison element 10 is triggered and the trigger 14 is activated through the H 13 element.

The trigger complex signal is transmitted to control register 2 for recording the response code and through decoder 1 to the common computer bus. The computer removes the sync signal by completing the word recording and, after removing the response sync signal, repeats the cycle to record the next word in the device of the peripheral system.

The meaning of response codes stored in register 2 can be read by computers when accessing this register.

Any of the peripheral devices of the subscriber can set the request in the block 3 shortings. The request signal enters the common computer bus from block 3 if the request signal coincides with the corresponding signal. The preload resolution is stored in register 2. Block 3 performs the operation of capturing the common computer bus and transmits the corresponding interrupt vector to the computer.

Claims (2)

1. A device for interfacing a subscriber computer, comprising a decimator, a control register, an interrupt unit, a switch, and a switch register, the device inputs for connecting the synchronization output and the first and second address outputs of the computer are connected respectively to the synchronization input of the interrupt unit, and the control inputs of the switch and with the first input of the decoder the second input of which is connected to the output of the device for connecting the first address address of the subscriber and the first output of the switch, the output of the register switch is connected to the coding input of the interrupt block and to the third input of the decoder, the first one, the second outputs of which are connected respectively to the device output for connecting the computer synchronization input and the first synchronization input of the control register, the first information output of which is connected to the mask interrupt block input, input and output interrupts of which are connected respectively to the input of the device for connecting the output of a subscriber's talk, and with the output of the device to connect the input of a computer's breaks, the second the switch stroke is connected to the output of the device for connecting the second address input of the subscriber, the input of the device for connecting the information output of the computer is connected to the first information input of the control register and the output to the device for connecting the information input of the subscriber, the input of the device for connecting the information output of the subscriber is connected to the output of the device for connecting informational 0 of the computer input and with the second information output of the control register, the second information input of which is connected to the input of the device for connecting the first synchronization output abo nent, different THAT, in order to improve performance, the mask register and the sampling block are entered into it, and sometimes the third decoder outputs are connected 0 with the synchronization input, respectively, of the mask register and the first synchronization input of the sampling unit, the information output of which is connected to the fourth input of the decoder and the second synchronization input of the control register, the input of the device for connecting the information output of the computer, the output of which is connected 0 with the information input of the sampling unit, the sampling output and the second synchronization input of which are connected respectively to the output of the device for connecting the subscriber sample input and to the output of the device for connecting the second synchronization output of the subscriber. 2. A device according to claim 1, characterized in that the sampling unit comprises a comparison element, an AND element, a trigger, an OR element and an AND element block, the information input of the block connected to the first inputs of the comparison element and the AND element block, the second input of the comparison element and the input of the element OR is connected to the second synchronization input of the block, the second input of the block of elements AND is connected to the first synchronization input of the block, the output of the block of elements AND is connected to the output of the block selection, the first, second inputs and output of the element AND are connected respectively to the outputs and the OR element and the comparison element and with a single trigger input, zero input and output of which are connected respectively with the output of the OR element and with the information output of the block ... . five AT 0 five Op5lZ Ot6l1 FromM 13 S il U MAU KSA.7 .2