SU1580365A1 - Device for processing inquiries - Google Patents

Abstract

The invention relates to computing and can be used in digital computing devices with non-active, independent subscribers. The purpose of the invention is to expand the functionality by providing a service mode for independent subscribers. The request processing device comprises a decoder, a memory unit, a counter, three comparison circuits, five registers, four AND elements, three triggers, a decoder, a group of AND elements, four OR elements, a switch and a delay element. The device allows independent subscribers to be serviced, requiring an individual response signal to the request and increases the efficiency of masking control. 1 hp ff, 2 ill.

Description

The invention relates to computing technology and can be used in digital computing devices with several active, independent subscribers.

The purpose of the invention is to expand the functionality of the device by providing a service mode for independent subscribers,

Figure 1 shows the block diagram of the device; figure 2 - structural diagram of the switch.

The device contains device information outputs 1, device interrupt output 2, memory block 3, counter 4, trigger 5, registers 6 and 7, AND elements 8 and 9, group 10 response outputs of the device, input 11 confirming device information, comparison circuit 12, registers 13 and 14, circuits 15 and 16 comparisons, elements AND 17 and 18,

register 19, group of elements AND 20, elements OR 21-23, decoder 24, triggers 25-27, delay element 28, group 29 of the device's request inputs; device information inputs 30, device address address group 31, device start input 32, device reset input 33, device clock input 34, device priority value inputs 35, device mask inputs 36, device interrupt confirmation input 37, switch 38.

The switch 38 (figure 2) contains a group of elements And 39, the decoder 40, the element OR 41, the register 42.

The device works as follows.

The device is reset beforehand by applying the corresponding signal to input 33. This leads to

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with

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that registers 42, 13 and 19 and triggers 5.25-27 go to the zero state. Reset trigger 5 with its output signal closes elements 8 and 9, preventing the passage of clock signals through them. In this case, the survey of subscribers does not occur. However, the request signals to the request input group 29 are written to the register 42 by the clock signals input to the clock input 34. The reset trigger 25 closes AND elements of the group 20 with its output signal, preventing the response signals from passing to the group 10 of the response outputs of the device. Reset trigger 26 does not generate an interrupt signal at the output 2 of the interrupt device. Reset trigger 27 prevents the flow of information from the outputs of the decoder 24 to the group of outputs 1 of the device. In addition, the trigger 27, with a signal from its inverted output, opens element I 18 at the corresponding input. After resetting the device, the corresponding information is recorded in memory block 3. In this case, the cell address of the memory block 3 is set via counter 4, the corresponding code is written into it through the group 31 of the device's address inputs, priority information, masking codes, etc. is fed as one data word to the information inputs 30 of the device. Then, the corresponding information is recorded in registers 6 and 7 via inputs 35 and 36.

After these procedures, the device is started up by applying the appropriate signal to the start-up input 32 of the device. In this case, the trigger 5 is set to one state, opening its output signal elements 8 and 9, and the clock signals through the clock input 34 of the device begin to flow to the inputs of the elements 8 and 9 and the register 42 of the switch 38.

The clock signals passing through the open element I 9 are fed to the counting input of the counter 4, transferring it to the next state. Thus, the counter produces a sequential interrogation of the cells of the memory block 3, the information from the output of which is fed to the inputs of the comparison circuits 12, 15 and 16 and the registers 13 and 14. In addition, the code from the output of the counter 4 is fed to the input

five

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five

0

five

five

0

five

the decoder 40, which produces a consistent poll of the outputs of the register 42 requests, opening the corresponding elements And 39.

If there are requests, the corresponding signals from the outputs of the register 42 are received through the corresponding elements AND 39 and through the element OR 41 to the inputs of the elements AND 17 and 18, opening the latter by means of the corresponding inputs. Item 17 is also open through other inputs if the following conditions are met: Comparison circuit 16 detects that the masking part of the control word does not match the mask code recorded in register 7, circuit companion 12 detects that the priority of the polled subscriber in the corresponding the part of the control word, above the priority, recorded in register 13, the comparison circuit 15 detects that the request is a priority. Those. the corresponding part of the control word coincides with the code recorded in register 6. If these conditions coincide, the clock signal, having inverted and passed through the element 8, passes through, and then writes the request signal into the register 19 through the element 17, resets the trigger 25 or confirms its zero state, writes to the register 13 the priority of the new request and sets the trigger 26 to the one state, the output of which generates an interrupt signal at the output 2.

Counter 4 continues to enumerate the requests of subscribers, not waiting for the response of the servicing computer. If, before the interruption confirmation signal from input service 37 arrives, another unmasked interrupt request with a higher priority is detected at input 37, then this priority is recorded in register 13. Requests with lower priority are ignored.

After the service device sets an interrupt acknowledgment signal to input 37, trigger 26 is cleared and the interrupt signal from output 2 is removed. In addition, the interrupt confirmation signal is set to one state trigger 25, the output of which opens the AND elements of group 20. This leads to the formation of a response signal at the corresponding output of group 10 of the device from the query signal recorded in register 19, the servicing computer reads the information about the subscriber number from the outputs of group 10 of the device and switches to Mu service. The subscriber, having received a response signal from the outputs of the device group 10, switches to the service mode.

In addition, at the same time, the AO decoder can interrogate the request for extra-priority service, i.e. maintenance that does not require the intervention of the servicing computer. The conditions for such a request are as follows: there is a service request, then the AND 1 8 element is opened by the output signal of the OR 41 element, the comparison circuit 16 detects that the masking part of the control word does not correspond to the mask code recorded in register 7. The comparison circuit 15 detects that the request is non-priority, i.e. the corresponding part of the control word does not coincide with the code recorded in register 6. When these conditions coincide, AND 17 is closed by the output signal of the comparison circuit 15, and AND 18 is open. Then, the inverted clock signal from the output of the AND 8 element passes through the AND 18 element, writes the information part of the control word to the register 14 and sets the trigger 27 to one state. The signal from the direct output of the trigger 27 permits the operation of the decoder 24, at the corresponding output of which. Go. is an information signal, coming to the output 1 of the device group. In addition, the signal from the inverse output of the trigger 27, delayed by the delay element 28 for the time required to write information to the register 14 and set the trigger 27 to a stable unit state, closes the element 18, preventing further change of information in the register 14. The device, having received information from the output of group 1, begins servicing the subscriber making an extra priority request, and issues a signal confirming the information to the input 1 1 of the device. This signal resets the trigger 27 to the zero state, which causes the opening of the element And 18 at the corresponding input and the prohibition of the operation of the decoder 24, which removes the information signal from the corresponding output of the 1st group. After

This may be repeated off-site service.

At the end of the priority service, the servicing computer makes the initial installation of the device, sending a reset signal to the device input 33, and the subscriber removes the request signal. Then the computer starts up the device, having given the corresponding signal to the input 32 of the device. If during servicing a subscriber a priority request is received with a higher priority than the served one, then the operation of the device proceeds in the manner described above. At the same time, resetting the trigger 25 causes the closure of the AND elements of group 20 and the removal of the corresponding response signal from the output of group 10. The subscriber who has lost the response signal goes into standby mode, without removing the request signal. The service computer will retain the necessary information about the previous service and proceed to the service of a higher priority request. Upon completion of the service of this request, the servicing computer performs the initial installation of the device and waits for the next interruption.

Upon receiving an interrupt, the servicing computer issues an interrupt acknowledgment signal and compares the information on the last suspended service with the information taken from the output of group 10. If it is determined that the answer signal corresponds to the subscriber whose service was interrupted last, then this service continues until the end of the service or before the next interruption of the higher priority request. If it is determined that the response signal does not correspond to the subscriber whose service has been interrupted last, then obviously this response signal corresponds to the subscriber with a higher priority request, the service of which the computer starts. Further operation of the device continues as described above.

Claims (1)

1. A request processing device comprising a memory block, a counter, a first trigger, a first comparable circuit, two registers, two AND elements, a switch, a decoder, the group of information inputs of the memory block is a group of information inputs ( device, a group of information inputs. the counter is a group of address inputs of the device, the outputs of the counter are connected to the group of address inputs of the switch and the memory block whose outputs are connected to the first group of inputs of the first comparison circuit and the information inputs of the first and second registers, the outputs of the first register are connected to the second inputs of the first comparison circuit, the output of which is connected to the first input of the first element And, the second input of which is connected to the output of the switch and to the first direct input of the second element And, in The direct input of which is connected to the third input of the first element AND, the fourth input of which is connected to the inverse input of the second element AND, the record entry of the first register is connected to the installation input 1 of the first flip-flop, the output of which is the interrupt output of the device, the outputs of the second register connected to the inputs of the decoder, the group of outputs of which is the group of information outputs of the device, the group of information inputs of the switch are request inputs of the device, characterized in that the functionality of the device by providing a service mode for independent subscribers; the third, fourth and fifth registers, the second and third triggers, the third and fourth AND elements, the AND element group, four OR elements, the second and third comparison circuit, the delay element, are introduced into it; moreover, the group of outputs of the switch is connected to the group of information inputs of the third register, each output of the group of outputs of which is connected to the first input of the element of the same name AND group, the outputs of which comprise a group of response ones of the device’s moves, the input of the second trigger set in I11 is the start-up input of the device, the output of the second trigger is connected to the forward input of the third element I and the first input of the fourth element I, the output of which is connected to the counting input of the counter, the clock input of the device is connected to the control input switch, with the direct input of the third element And, and with the second input of the fourth element And, the output of the third element And is connected to the fifth input of the first element And with the third direct input of the second element I, the output of which is connected to the recording input of the second register and the installation input to 1 of the third trigger, the direct output of which is connected to the control input of the decoder, the output of the first element I connected to the recording input of the third register, with the first input of the first the OR element and with the installation input in 1 of the first trigger, the device reset input is connected to the reset inputs of the switch, the second trigger, the first and third registers with the second input of the first and with the first inputs of the second and third elements of the IL , the output of the third element OR is connected to the reset input of the third trigger, the inverse output of which through the delay element is connected to the fourth direct input of the second element AND, the second input of the third element OR is the device information confirmation input, the device interrupt confirmation input is connected to the installation input 1 the fourth trigger and with the second input of the second OR element, the output of which is connected to the reset input of the first trigger, the output of the second OR element is connected to the reset input of the first trigger, output a quarter The second trigger is connected to the second inputs of elements AND groups, the information inputs of the fourth register are a group of inputs of the device priority value, the outputs of the memory block are connected to the first inputs of the second and third comparison circuits, the outputs of the fourth register are connected to the second inputs of the second comparison circuit whose output is connected with the inverse input of the second element And, the outputs of the fifth register are connected to the second inputs of the third comparison circuit, the output of which is connected to the second direct input of the second element And, nye inputs of the fifth register are input group mask device vho1- counter recording rows and the fourth and fifth registers included in the group address inputs of the device. 2, The device according to claim 1, wherein the switch comprises a register, a decoder, a group of AND elements, an OR element, the group of information inputs of the register is a group of information inputs of the switch, a group of inputs of the decoder is a group of address inputs the switch, each output of the decoder is connected to the first input of the same name AND group, the outputs of which are a group of outputs of the switch and connected to the inputs of the OR element, the output of which is the output of the switch, the second input of each element of the group which is connected to the output of the same register bit The clock input and the reset input of which are the control input and the reset input of the switch, respectively. 21 25 -2 FIG L To El. 17.18 Fig2