SU1478222A1 - Computer/external device interface - Google Patents

Abstract

The invention relates to computing and can be used to interface a multi-speed source and receiver of information. The aim of the invention is to increase speed. The device contains an address decoder, a status register, an interrupt block, a switching register, two address counters, an array counter, a control unit, two OR elements, a delay element, four buffer registers, two memory blocks, two registers. 1 hp f-ly, 4 ill.

Description

one

The invention relates to computing and can be used to interface a multi-speed source and receiver of information.

The aim of the invention is to increase speed.

Figure 1 presents the block diagram of the device; on. Fig. 2 is a functional block diagram of the control unit; FIG. 3 is a functional block interrupt diagram; 4 shows a system using the proposed device.

The device (Fig. 1) contains the address decoder 1, the state register 2, the interrupt unit 3, the switching register 4, the address counters 5, the array 6 and the address 7, the control unit 8, the OR element 9, the delay element 10, the buffer registers 11 and 12, second register AND (receiver), memory blocks 14 and 15, buffer registers 16 and 17, element OR 18, first register 19 (transmitter), computer bus 20, inputs and outputs 21-95, page register 26.

The control unit 8 (FIG. 2) comprises a pulse generator 27, an AND element 28, a shift register 29, a trigger 30, an AND element 31, a shift register 32, a trigger 33, a multiplexer 34, strokes and outputs, an input output 41.

Interrupt unit 3 (FIG. 3) contains an OR 42 element, AND elements 43 and 44, a multiplexer 45, a trigger 46, a counter 47, a register 48, a pulse generator 49, inputs-outputs 50-54. 4, computer 55, external

device 56, the proposed device 57.

Counters 5 and 7 addresses are designed to record the starting address and form the current address of the polled external devices during operation of the device.

The array counter 6 is designed to record information about the number of external devices polled and generate a polling mode termination signal supplied to register 2

(L

states and interrupt block 3 as a Ready signal.

Interrupt unit 3 is designed to organize a program interrupt mode both at the end of the polling cycle of external devices and by the Interrupt Request signal from external devices, which is sent to interrupt unit 3 via chains 21j, 21,.,.,

21.

But the chains of organizing the program interrupt mode and transmitting the interrupt vector address are interrupted by the interrupt unit 3 to the computer channel.

Switching register 4 is designed to record information controlling the operation of buffer registers 11, 12, 16, and 17, counters 5-7, and register register 26.

The control unit 8 is designed to generate signals to the receiver of the information supply.

The device works as follows.

After the power is turned on by the initial signature, all elements of the device are reset. At the outputs of the switching register 4, a control iodine is formed, according to which the registers counters 5-7 and the register 26 of the page are set to the information recording mode. The computer, accessing the device, writes in the page register 26 of the page the code identifying the page number of the memory blocks 14 and 15: in the address counter 7, the code determining the initial number of the external device; in address counter 5, a code defining the starting address of memory blocks 15 and 14 with respect to the page code and corresponding to the starting number of the external device; In the array counter 6, a code defining the number of external devices subject to an olros.

Next, referring to the device, the computer writes a code to the switching register 4, according to which the buffer 11 and 17 registers open, the buffer registers 12 and 16 are blocked, the counters 5-7 are switched to the counting mode, and the register 26 of the page in reading mode. Thus, through the open buffer registers 11, the memory block 14 is connected to the computer channel, and the memory block 15 via the open buffer registers 17 to the internal channel of the device. The computer, in accordance with the program, writes into the memory block 14 information that controls the external devices.

Moreover, the access to the memory block 14 is performed by referring to the device register register 26, i.e. in the address cycle, the address register 26 is opened by the address decoder 1 signal, and the code defining the page number is fed to the memory block 14 through the open buffer registers 11. The page cell number is fed to memory block 14 directly through the computer channel through the buffer registers 11. After the control information is written to memory block 14, the device again accesses the device and writes the code in switch register 4, according to which the buffer registers are opened 12 and 16 and the buffer registers 11 and 17 are blocked. After the switching of the block

14 with the prepared control information is connected to the internal channel of the device, and the unit

15 spam - to the computer channel. Next, the computer, accessing the device, writes into the state register 2 bits the Enable Interrupt, which is transmitted

in block 3, interrupt on input 52 and block 8 of control on input 36, being for it a trigger signal. In block 8 of the control, the pulse generator 27 starts operating. The pulses from the output of the generator 27 pulses through the element 28 are fed to the shift register 29, where the control signals are formed, corresponding to the output cycle. These control signals through the multiplexer 34 are fed to the internal channel of the device. The multiplexer 34 is controlled by a flip-flop 33, to the input of which, at input 38, a signal of the initial setup arrives, and at input 23 - a signal from the output of the delay element 10. Under the influence of the generated control signals, the memory unit 14 exposes the information of the memory cell, determined by the address at the output of the register-counter of the address 5, and the signal of the TLV (CIP), indicating that the data is on the highway. On the signal of the HTV (SIP), coming to the inputs of the trigger 30 and the shift register 29, the control unit 8 generates a signal,

which through the element OR 9 enters the synchronous input of the register 13 of the receiver) and the input of the element 10 of the delay. The memory cell information is written into register 13 (receiver). In the control unit 8 by the signal of the FCV (the CIP switches the trigger 30 so that the inhibit potential arrives at the AND 28 element, and the resolving potential arrives at the AND 31 element.

The output signal of the delay element 10 is gating for all external devices and through the OR 18 element enters the synchronous input of the register 19 (transmitter). This signal in register 19 (transmitter) records information (from input 25) of the external device, whose address is determined by address counter 7 (output 22). In addition, the external device receives control information from register 13 (output 24) using this signal. The same signal is fed to the control unit 8 at the input of the trigger 33, which controls the multiplexer 34. At this point, the control unit 8 generates the control signals corresponding to the Input cycle. In this cycle, information from register 19 (transmitter) is recorded in memory block 14 at the address determined by address counter 5. At the end of the cycle Input unit 8 control generates a signal (output 40), which is fed to the counting inputs of counters 5-7. The same signal switches the trigger 33. The trigger 30 switches by the signal of the TOV (CIP) after writing the information to the memory block 14. Counters 5 and 7 of the address are incremented, forming the address of the next external device and the corresponding memory cell. Next, the information I / O cycle repeats until a signal is output at the output of array 6, indicating that all external devices are polled. Thus, in the process of polling the external devices, the control information in the memory block 14 is replaced with the state information of the external devices.

The output signal from the array counter 6 goes to control unit 8 at input 35 and blocks generator 27. This same signal goes to block 3 interrupts at input 54 to the element

50

5 0 5 0 5 0 5 0

five

And 43, At the second input of the element And 43, the Enable Interrupt (ROR) signal is received from the state 2 register (input 52). The combination of these two signals at the output of the element And 43 is formed by the signal The requirement of interruption, which through the element OR 42 enters the computer channel.

The signal from the output of counter 6 of the array, in addition, enters the state register 2. The transition to the service routine, computer, cheat, status register 2, determines that the interrogation of external devices is over. The computer re-switches the buffer registers in such a way that the memory block 14 with the information recorded in it from external devices is connected to the computer channel. Further, the computer is engaged in processing the received information. A new polling cycle for external devices starts after writing the state 2 bit into the Enable Interrupt Allow register.

In the event of a critical situation in one of the external devices, it generates an Interrupt Request signal, which is fed to the interrupt block 3 through the inputs 21 to the inputs of the multiplexer 45.

The control code to multiplexer 45 comes from counter 47, the counting input of which is connected to the output of high-frequency generator 49 of pulses. The generator 49 is started from the trigger 46, the information input of which receives signals from state register 2 (RPR) at input 52 and from the output of multiplexer 45. The code from the output of counter 47 enters state register 2 (output 51) and is address of the external device that requested the interrupt. In addition, the signal from the output of the multiplexer 45 enters the state register 2, characterizes the interrupt upon request of the external device, and into the control unit 8 on the input 37, blocking its operation.

In the interrupt processing routine from an external computer device, commutes, divides the registers so that the computer channel is connected to the internal channel through open buffer registers 11 and 12 (16 and 17). In this case, referring to the registers 13 and 19 and the counter 7, the computer

directly polls the external device that requested the service, and generates a control code for it, i.e. the device allows, if necessary, to carry out a direct exchange mode between the computer and external devices.

In the autonomous mode of operation, the exchange of information between the computer and the external device is initiated by the computer, and the information is transmitted and transmitted under the control of the device in such a way that one of the device’s memory blocks participates in the exchange. The computer at that time continues to operate in accordance with the program, using the second memory block, which is connected directly to the computer channel via software-switched buffer registers. Thus, the exchange of information between the computer and external devices is carried out without the participation of the computer, with the exception of the computer accessing the interface device for recording the switching codes and the mode.

Claims (2)

Invention Formula 1. A device for interfacing a computer with external devices, comprising a first memory block, a control unit, two address counters, an array counter, an address decoder, a first register, a delay element, two OR elements, the output of the delay element being an output, connections to external gate inputs ten 15 30  , 782228 The addressable bus of the computer, the first information input of the status register and the output of the interrupt unit interrupt are input and output of the device for connecting respectively to the interrupt enable output and the interrupt request input of the computer, the group of inputs of the interrupt request block of the device for connecting to the interrupt request outputs of external devices, the group of outputs of the second address counter forms a group of device outputs for connection to the address inputs of external devices, info The output output of the second register is the output of the device for connection to the information inputs of external devices, the installation input of the control unit is the input of the device for connection to the output of the computer’s initial installation, the first output of the address decoder is connected to the control input of the state register, information the input of which is connected to the address output of the interrupt unit, the input of the resolution of the interruption of which is connected to the first input of the logic condition of the control unit and to the information output of the register tra state, a second information input of which is connected to the second input of the logic control unit conditions and a yield of interrupting an interrupt request unit allowing input of which is connected with the third informational input of the register state, a yield of the array and counter 20 25 devices, information input first-40 with the third input of the logical condition register is the input of the device for connection to the information outputs of external devices, characterized in that increase the speed, in which the input of which are connected respectively with the second memory block, the status register, the page register, the interrupt block, the switching register, four buffer registers, the second register, the information output of the state register, the information input / output of the interrupt block, the information inputs of the first and second address counters, the array counter the address decoder, the register of the page, the register of switching, the first information inputs-outputs of the first and second buffer registers form the input-output of the device for connecting to the control information unit, the first output of which connected to the counting inputs of the first, second counters of the address and the array counter, synchronous inputs 0 five the second, third and fourth outputs of the address decoder, the fifth output of which is connected to the synchronized input of the page register, the information output of which is connected to the information inputs of the first and second buffer registers, the second information inputs-outputs of which are connected to the address inputs and the information inputs of the first and second memory blocks, respectively, with the first information inputs / outputs of the third and fourth buffer registers, respectively, the second information inputs / outputs of which are connected with the information outputs of the first register, the first counter, with the input output of the control unit, with the information input of the second register, the synchronous input of which is connected to the output of the first OR element and to the input of the delay element whose output is connected to the first input of the second OR element and the fourth input of the logical conditions of the control unit whose second output is connected to the first input of the first OR element, the second input of which is connected to the neck input of the address decoder, the seventh output of which is connected to the second input v OR, whose output is connected to the first register sync input, the eighth output of the address decoder is connected to the switching register synchronization input, the first output of which is connected to the write / read input of the page register and the input of the first and second counters of the address and array counter, The second-fifth outputs of the switching register are connected to the write-read inputs of the first and fourth buffer registers, respectively. 2. The device according to claim. characterized in that the control unit contains a pulse generator, a multiplexer, two shift registers, two triggers, two AND elements, the start input and the first, second inputs of the pulse generator 5 5 5 0 five The first, second and third inputs of the logical condition of the block are synchronized, the first trigger's synchronous input is the fourth input of the logical condition of the block, the first trigger's zero input is connected to the second trigger's zero input, and the multiplexer information output and the second trigger's third input are connected With the input of the operation mode of the first shift register, is the input-output of the block, the first outputs of the second and first shift registers are the first and the second the outputs of the block, while in the control unit the output of the pulse generator is connected to the first inputs of the first and second elements AND, the second inputs of which are connected respectively to the single and zero outputs of the second trigger, and the outputs to the synchronous inputs of the second and first shift registers, the second output of the first the shift register is connected to the information input of the second shift register and to the first information input of the multiplexer, the second information output of which is connected to the second output of the second shift register, the first output of which is connected to the setup input of the first shift register and the information input of the first trigger, the output of which is connected to the input of the operation mode of the second shift register and to the control input of the multiplexer. b / WITH hi q and Ґ.г chg Јi l-i UK 91 02 Phage. 2 FIG. s 55 Fig.h