SU734695A1 - Single-crystal microprocessor - Google Patents

Description

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The invention relates to automation and computing technology and is intended to implement problem-oriented and specialized electronic computers.

A microprocessor is known that contains an arithmetic logic unit, a control unit, a register unit, an address data line, an input / output unit, data buses, address buses, and control buses 1.

The disadvantage of this microprocessor is the computational power in a single-processor version and the complexity of organizing a multi-microprocessor system, a large range of additional large integrated circuits (LSIs) for building a functionally complete computational tool.

The closest to the invention is a single-chip microprocessor containing an I / O unit, a memory unit, a switch, a row decoder, a column decoder, an address register, an operation code register, an arithmetic logic unit, a control unit, and the inputs of the input / output block are microprocessor inputs.

The outputs of the I / O unit group are the microprocessor outputs, the information output of the I / O unit is connected to the first inputs of the switch, the arithmetic logic unit and the operation code register, and the control output of the I / O unit is connected to the first input of the control unit, the second input of which connected to the output of the operation code register, and the output of the control unit is connected to the second inputs of the switch and the arithmetic logic unit, the first and second groups of outputs of the address register are connected to the groups of inputs the row decoder and column decoder, and the address register input group is connected to the first switch output group, the second output group of which is connected to the write and read inputs of memory block 2. In addition, the device contains a persistent memory, row and column address decoders, registers of the address of a row and a column2Qa, block of operational registers.

Device flaw -. the complexity of microprocessor circuits and the presence of large redundancy in equipment, which ultimately reduces the computational capabilities of the microprocessor and makes it difficult to place it on a single chip. The purpose of the invention is to simplify the microprocessor. The goal is achieved in that it contains a comparison circuit, a column shift register, a row shift register whose inputs are connected to the outputs of the row decoder, and outputs are connected to memory inputs, columns shift register inputs are connected to the outputs of the column decoder, and the outputs are connected to the inputs of the switch group, the control inputs of the row shift register and the column shift register are connected to the output of the control unit and the output of the comparison circuit, the first input of which is connected to the output of the address register, and the second input p Connected to the control output of the column shift register. - In addition, the I / O unit contains a convolution register, a sweep register, a mask register, a comparison circuit, a switch, the inputs of the first switch group are inputs to the I / O block, the first output of the switch is connected to the input of the convolution register, the output of which is informational output of the I / O unit and connected to the information inputs of the sweep register, mask register and comparison circuit, the second output of the switch is connected to the second input of the comparison circuit, the third input of which is connected to the control input regis The mask path and the third output of the switch, which is the control output of the I / O unit, the input of the switch is connected to the output of the mask register, the fourth output of the switch and the output of the scan register are the outputs of the I / O unit group. In this case, the memory block contains a matrix of operational and fixed memory cells, with the first input of each permanent or operational cell of the memory block connected to the corresponding input of the next cell located in the same column and connected to the corresponding input of the first group, and the second the input of each constant or operational cell of the memory unit is connected to the corresponding input of the next cell located in the same line and connected to the corresponding input of the second group. The drawing shows a diagram of the proposed device. The device contains a register of 1 address, a circuit 2 of comparison, a decoder of 3 lines, a register of 4 lines, a block of 5 memory operative. memory cell 6, fixed memory cell 7, switch 8, column shift register 9, 10 column decoder, arithmetic unit 11, operation code register 12, control unit 13, input-output unit 14, convolution register 15, sweep register 16 , mask register 17, comparison circuit 18, switch 19, first output of output group of input-output unit 20, input group of input-output unit 21 and 22, second output of output group of input-output unit 23, information output of input-output unit 24, control output of the input-output unit 25. The device works as follows. The execution of commands in the microprocessor includes the process of sampling p-binary bits at a given address from memory block 5 (p-binary bits are either part of the program or part of the operational information). The p-bits bits are sampled using the column shift register block 9, which contains three combined shift registers. The first shift register stores the column address of memory block 5 corresponding to the current command. The second shift register stores the address of the column of information read from the operational memory, and the third shift register stores the recordable one. Block 4 of the shift row register also contains three shift registers. Their purpose is similar to the purpose of block 9, only for storing and modifying addresses of strings. To read the p-bits from memory 5, information is read from all memory cells in a row whose address is set on register 4 (on one of the row address shift registers). On read write buses, the contents of the operational and fixed cells of the row enter the switch 8. In switch 8, n-binary bits are selected from the information of the entire line. The address of the selected p-bits bits is set on one of the shift registers 9 column shifts. To write the p-binary bits to the memory block 5, they are pre-recorded in the switch 8. Then, from the memory block 5, the entire line of information is read, the address of which coincides with the address of the line of the written p-binary bits. Then the p-binary bits are inserted into the switch 8 in the information row at the specified column address, and thereafter, the information of the entire row is written into the memory block 5 at the specified row address. The forwarding command word contains the forwarding operations code and the A1 and A2 addresses in binary code. The execution of the command begins by reading the operation code to the switch 8 in the manner described. From switch 8, the opcode is sent to opcode 12. Here, the operation code is decrypted and the control unit 13 generates control signals corresponding to this command. The implementation of this command is as follows. From block 5 of memory, the next part of the command, address A1, is selected and transferred to address register 1. Then the address A1 goes to the decoder of 10 columns and is converted into a positional code, i.e., a signal is received at the input of the register of 9 columns only by one address input. This signal is recorded in the second shift register of block 9. The address of the line in the second shift register of block 4 is recorded in a similar way. Then, the address A2 is selected from the command word. Address A2 sets the third shift register E and the third shift register 4 in the same way as A1. After the row and column addresses have been established in the respective registers, information is transferred from memory block 5. For this, the information is first read into switch 8 at one address, and then transferred from the switch to memory block 5 in the manner described, at different addresses. The information is sent over the p-binary bits until the comparison circuit 2 is triggered and the control unit 13 issues the appropriate control signals for sampling the next command.

The operation of the microprocessor in performing an arithmetic operation, for example, adding the tetrads of two operands located at address A1 and A2, recording the result at address A2, is performed as follows.

The command word contains the operation code and information addresses A1 and A2. First, the command is selected and the shift register of rows and columns is set up in a manner similar to the execution of a transfer command. Then, from the memory block 5, the tetrad of the first operand is selected to switch 8. From this block, the tetrad is transferred to the arithmetic logic unit 11. Then in block 11, the tetrad of the second operand is similarly sent and added. If a transfer is formed during the addition, the special transfer presence trigger in the arithmetic logic unit 11 is set to "one state, otherwise - to" zero. The result of the addition in block 11 is sent to the switch 8 and then to memory block 5.

When executing a command to transfer control (conditional transition), a transition is made to two different points of the program, depending on the condition — the state of the transfer trigger in the arithmetic logic unit 11. The command word contains the operation code and the transition address A1 in the case of a single state trigger the presence of the transfer. When the trigger state is "zero", the command following this one is executed. The execution of the command begins after decoding the operation code of the command, which is written to the operation code register 12. Then, the transfer presence trigger state is transmitted to control unit 13. This block analyzes the state of the trigger and, depending on it, generates a sequence of control signals. If the trigger is "in the single state, then the transition address A1 to the switch 8 is read from the command word. The address A1 is transferred to the address register 1. Then this address sets the address of the transition column in register 9 through the decipher of 10 columns, and through the decoder 3 of the address of the rows sets aa.res The transition jumps in register 4. The next program command is addressed to the specified address.

If the state of the trigger is zero, then the sequence of control signals will shift the addresses in registers 9 and 4, corresponding to the command following this one, and its selection for execution. Commands in which action is performed on variable length words are carried out using the comparison circuit 2 and the control unit 13 consisting of video tetrads located in the main memory cells 6 with the initial address of the first tetrad in the A1 array in the zone memory with starting address A2. The command word contains the operation code and the addresses A1 and A2 in binary code. When executing this command, the purpose of the comparison circuit 2 is as follows. Each address of a sample of information received at the input of comparison circuit 2 from the output of register 1 of address (in this case, A1) is converted to another address, A1, and

AI A1 + K,

where K is the number of n-bit words enclosed in operational cells of 6 memories with addresses A1 and A1. Thus, in this example, A1 A1 + 7. In addition, the A1 address in the comparison circuit 2 is converted from a binary code to a position code. To the other input of the comparison circuit 2, the current address is received from register 9.

If the current address and the address coincide (in example A1 O formed in the comparison circuit 2, the output of the comparison circuit 2 generates a comparison signal in the control unit 13.

It should be noted that the comparison circuit 2 is technologically performed similarly to the ROM matrix, which allows the module to record the required correspondence between the input addresses and the transformed ones in the matrix during the manufacturing process of the module. This allows you to vary the length of the information arrays processed in the module.

The execution of the command to transfer an array of eight tetrads is carried out as follows. The first n-bit word of the array, located at address A1, is sent to the operative cells of memory block 6 at address A2, similarly to the execution of the previously mentioned transfer command, but the execution of the command does not end there. In accordance with the control signals of the control unit 13, the shift of the column address, the register of 9 columns, is further shifted by one bit, in the direction of increasing the address of the column. After that, the second n-bit word of the array is sent, and then the transfer process continues until the comparison signal is output at the output of the comparison circuit 2. Thereafter, the process of executing this command ends. Similarly, the transfer operations are performed by the operations of arithmetic and logical processing of arrays of information. The presence in the module of an I / O unit 14 consisting of a convolution register 15, a sweep register 16, a mask register 17, a comparison circuit 18 and a switch 19 allows microprocessors to be interconnected to create computing systems on single-type single-chip microprocessors. During the operation of the system, the microprocessors exchange information with each other, and any microprocessor can be both a receiver and an information sensor. The information I / O mode is performed after the corresponding command is decrypted. Information output from the microprocessor is carried out as follows. First, the process of establishing the connection of this microprocessor with the information microprocessor occurs. For this, output 23 of the first group of outputs of the I / O unit produces a "call signal, and from the sweep register 16, output 20 of the I / O unit gives the microprocessor number with which compound. The microprocessor number is programmed. After receiving a response from the corresponding input 21 of the group of inputs of the I / O unit, the connection establishment process is considered complete. After that, information from memory block 5 through switch 8 is transmitted via information output 24 of the I / O block to sweep register 16. Received in register 16 n-bit information is converted into a serial code and in this form is transmitted to output 20 of the I / O block. The transfer process is terminated by the initiative of either a receiving or transmitting microprocessor. If, after issuing the "call and microprocessor-receiver number" signal, the response signal is not received, then the "call with microprocessor number" signal is issued until the response signal is received. The microprocessor receives the information as follows. In accordance with a software microprocessor, a mask code is sent from the memory block 5 to the mask register 17, which allows reception on one or the other or several INPUT channels. Receiving a call signal at the input 21 of the group of inputs of the I / O unit and the input number 22 of the group of inputs of the I / O unit, the number is sent to the comparison circuit 18. The coincidence of the number received at the input of the 22 groups of inputs of the I / O unit with the number established by the program. Circuit 18, means that the call handling refers to this microprocessor. In this case, the microprocessor sends a response signal from the output 23 of the second group of outputs of the I / O unit. The connection establishment process has ended. After this, information is received from input 22 of the group of inputs of the I / O unit. The information through the switch 19 enters the convolution register 15. In this register, the serial code is converted into an n-bit parallel code and then, via the information output 24 of the I / O unit through the switch 8, is written into the memory block 5. The presence of the address registers of rows, columns and a comparison circuit in a single-chip microprocessor allows one program command to specify an operation to process an array of information containing an arbitrary number of n-bit words. In the well-known single-chip microprocessors, a program from a number of commands is needed to perform a similar operation. For example, to move an array of information from one area of the operational zone to another, it is necessary to run a program consisting of the following commands: setting the address of the initial tetrad of the array, moving the tetrad of information, increasing the address to form the address of the next tetrad, comparing the address with the ending address of the array and exit from the program in the case of comparison. The calculation shows that the volume of the fixed memory increases by 3-4 times. In addition, when working with arrays of information, the device speed increases by 2 times by applying address shift registers and reducing the time it takes to execute one command instead. The use of a single-chip microprocessor with permanent and main memory cells makes it possible, during the development process, to optimally allocate the memory of the module to a permanent and operational zone, depending on the requirements of the tasks to be solved. This allows minimizing the number of microprocessors in the implementation of a specific computing tool. On the other hand, fixing the ratio between the constant and operational zones of the same in all microprocessors leads to either an increase in the number of modules or the need to increase the degree of integration on the chip to increase the total memory of the microprocessor, which significantly increases the cost of the tool.

The use of an I / O unit that allows working with other microprocessors over a single-wire communication channel makes it possible to reduce the number of input-output contacts of the BIS microprocessor by almost 4–8 times. This leads to an increase in the reliability of the device, and also allows an increase in the degree of integration of elements on the chip due to the vacated area of the contacts and output amplifiers. If the area of one contact is equivalent to 10 bits of RAM, and the amplifier is 15, then the use of the proposed I / O unit will increase the amount of RAM or fixed memory by 400 bits.

Claims (3)

1. A single-chip microprocessor comprising an input / output unit, a memory unit, a switch, a row descrambler, a column decoder, an address register, an operation code register, an arithmetic logic unit, a control unit, and the inputs of the input-output unit are microprocessor inputs, outputs I / O unit groups are microprocessor outputs, the information output of the I / O-output block is connected to the first inputs of the switch, the arithmetic logic unit and the operation code register, and the control output of the I / O block is connected to the first m input of the control unit, the second input of which is connected to the output of the operation code register, and the output of the control unit is connected to the second inputs of the switch and the arithmetic logic unit, the first and second groups of outputs of the address register are connected to the input groups of the row decoder and column decoder, respectively, and the group the inputs of the address register are connected to the first group of outputs of the switch, the second group of outputs of which is connected to the write and read inputs of the memory block, characterized in that, in order to simplify the microprocess ra, it contains a comparison circuit, a column shift register, a row shift register whose inputs are connected to the row decoder's outputs, and outputs are connected to the memory block inputs, column shift register inputs are connected to the column decoder outputs, and the outputs are connected to the group inputs the switch, the control inputs of the row shift register and the column shift register are connected to the output of the control unit and the output of the comparison circuit, the first input of which is connected to the output of the address register, and the second input is connected to the control output of the pe gistra shear column. 2. The microprocessor of claim 1, wherein the I / O unit comprising the convolution register, the sweep register, the mask register, the comparison circuit, the switch, the inputs of the first switch group are the inputs of the input / output block, the first output of the switch is connected to the input of the convolution register, the output of which is the information output of the I / O unit and connected to the information inputs of the scan register, the mask register and the comparison circuit, the second output of the switch connected to the second input of the comparison circuit, the third input of which is connected to the control input of the mask register and the third output of the switch, which is the control output of the I / O unit, input the switch is connected to the output of the mask register, the fourth output of the switch and the output of the scan register are the outputs of the I / O unit group. 3. The microprocessor according to claim 1, characterized in that the memory block contains a matrix operative and fixed memory cells, the first input of each permanent or operative cell connected to the corresponding input of the next cell located in the same column and connected to the corresponding input of the first group, and the second input of each constant or operative cell of the memory block connected with the corresponding input of the next cell located in the same line and connected to the corresponding input of the second group. Information sources, taken into account in the examination 1. Evreinov, E. V., Praigishvili, I. V. Digital atoms with a tunable structure. M., “Energie, 1974, p. 135-139. 2.Intel. 8048 EDN, 1976, No. 21, p. 48-89 (prototype).  . ..0 734695