SU1389011A1 - Switching device - Google Patents

Abstract

The invention relates to automatic switching and can be used in digital electronic automatic telephone exchanges for constructing a digital switching field, as well as in data networks. The purpose of the invention is to increase reliability and throughput and simplify the operation of the switch. To achieve the goal, a block for receiving commands 26, a block for transmitting commands 27, two decoders 19, 20, a buffer register 21, two registers 22, 23, a multiplexer 24, AND 25 are entered into the device. The block for receiving commands 26 contains the memory of input commands, the memory active (; and input paths, pointer memory, two registers, two multiplexers, two decoders, a trigger, two OR elements, three I.) The command transfer block 27 contains a memory of output commands, a pointer memory, a trigger-, multiplexer, register, element OR, three elements I. The switch operates in three modes: in the mode of switching information, in the mode of receiving commands, and in the mode of transmitting commands. 2 Cp f-crystals, 4 Il. C /)

Description

in the corresponding cycles is receiving information in block 26 receiving commands. If the input path is activated (a paging control command has arrived), all of the following information is transmitted to memory 7, including the following paging control commands intended for other switches. The activation of the input path is removed when a disconnect command is issued.

If the processor has written a confirmation command to command transfer unit 27, simultaneously with this, memory 62 (output instruction pointer) will be written 1. When reading 1 from memory 62, trigger 68 will write 1 which means that register 21 will be in tact The TOR, and register 69 is open, skip information to bus 28. Register 21 is opened only when O is read from memory 62, and 1 is read from one of bits of memory 8, which determines the fact that the path has been closed, 1. If; the path is not connected (at the output of the register 22 connected to the element I 65 - O), the register 21 is closed . In this case, the information in the converter 6 is recorded, which is defined as a disconnect command (all bits are left). This provides automatic disconnection of the path by all switches of the switching floor.

The mode of receiving commands.

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The command assignment function is performed by the decoder 51. It selects two types of commands: a control command for the disconnection and a command for disconnection. In on

command control proklyucheniem. During the path activity, the descrambler 51 does not respond to incoming control commands and responds neither to the disconnecting command, but in the inactive state

the state of the input path, the decoder 51 does not respond to the disconnect commands, and responds to control commands that follow this path. This ensures the selection of only those commands to which the switch must respond, or rather, the processor that controls the switch 1-1 switch. Other

the commands are passed to the memory 7..

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Upon detecting the command, a set of - - blocks 51, 55, 56 generates recording pulses arriving at the recording inputs of memories 48-49 and through element SHSh 57 and decoder 52 to one of the recording inputs of the pointer 50 of the input commands, where 1 is accumulated, 49 commands received in memory. The processor, having read the information from memory 50 through block 10, knows immediately about several incoming commands, the address at which commands arrived in memory 49 is determined by the set of the address at which reading 50 was read, and the digit number in which 1 is written. Then the processor at this address can read the command from memory 49 and execute it. The result of the execution should be expressed in writing in memory 8 of the connections of the corresponding information: either the connection of the path with a specific commutation or the shutdown of the path. At the same time

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the output of which is connected to the control input of the buffer register, the control output of the second register connected to the enable input of the command transfer unit, the first clock output of the synchronization unit connected to the first clock inputs of the command receiving and transmitting units and the clock input of the voice memory, the second clock output block synchronization is connected to the second clock input of the command receiving unit, the third clock output of the synchronization unit is connected to the third clock input of the command receiving unit, and the second clock input of the command transmission unit and the second input of the AND element, and the address input of the memory of the connections is connected to the output of the second multiplexer.

2, the switch according to claim 1, which is based on the fact that the command receiving unit contains a memory of input commands, a memory of activity of input paths, a memory of pointers, two registers, two multiplexers, two decoders, a trigger, two the OR element is three AND elements, and the information input of the block is connected to the information inputs of the memory of the input commands and the first decoder, the outputs of which are connected to the information input of the activity memory of the input paths and the inputs of the first OR element, whose output and the first clock input of the block through the first the element And connected to the control inputs of the memory of input commands, activity memory of input paths and the first input of the second OR element, the output of which is connected to the control input of the second decoder, the output of which is connected to the information input of the pointer memory, the output of which is connected to the information input of the first the register, the outputs of which and the second register are connected to the information output of the block, the first address input of which is connected to the first information input of the first multiplexer and the information input of the second a multiplexer whose output is connected to the address input of the activity of input paths, the output of which is connected to the trigger input, the output of which is connected to the control input of the first decoder, the sync input of the block is connected to the synchronous inputs of the first and second multiplexers, trigger and pointer memory, the second address block input is connected to the second

1-12

the information input of the first multiplexer, the output of which is connected to the information input of the second decoder and the address inputs of the memory of pointers and the memory of input commands, the output of which is connected to the information. the second input of the second register, the first control input of the block is connected to the first input of the second element And the first control input of the second register, the second control input of the block is connected to the first input of the third element And the first control input of the first register, the second clock input of the block is connected with the second input of the third element I, the output of which is connected to the second control input of the first register, the third clock input of the unit is connected to the second input of the second element I, the output of which is connected to the second control input of the second register and the second input of the second element OR.

3. The switch according to claim.

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The command transmission block contains the output command memory, pointer memory, trigger, multiplexer, register, OR element, three AND elements, the information input of the block connected to the information input of the output commands memory, the output of which is connected to the information register. the output of the block, the first and second address inputs of which through a multiplexer are connected to the address inputs of the memory of output commands to the memory of pointers, the sync input of which is connected to the sync input of the block and the synchronization input of the multiplexer The first and the clock inputs of the block through the first element AND are connected to the control input of the memory of output commands and the first input of the OR element, the output of which is connected to the control input of the pointer, the output of which is connected to the first input of the trigger, the outputs of which are connected to the first inputs respectively, the second and third elements And the second clock input of the block is connected to the second input of the trigger and the second inputs of the second and third elements And, the resolution input is connected to the third input of the third element And, the output of which one with the charging output of the unit, the output of the second element I is connected to the control input of the register and the second input of the ele; ment or.

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Claims (3)

Fore one. A switch containing serial-parallel converters, the information inputs of which are connected to the group of information inputs of the switch, parallel-serial converters, the outputs of which are the outputs of the switch, the first multiplexer, the output of which is connected to the address input of the speech memory, the connection memory, the synchronization block, the synchronization output of which is connected with the sync input of the first multiplexer, and the clock inputs with the synchronization inputs of the switch, the interface unit ^ connected by a two-way communication view with a computer exchange bus, characterized in that, in order to increase reliability and throughput, an instruction receiving unit, an instruction transmitting unit, two registers, a buffer register, two decoders, elec 1389011. ₁₀ ment And, a multiplexer, the outputs of the serial-parallel converters, the information output of the command transmission unit and the output of the buffer register are connected via the data bus to the information inputs of the first register and parallel-serial converters, the output of the synchronization unit path number is connected to the first information inputs of the first and second multiplexers, with the first address inputs of the command receiving unit and the command transmitting unit and the information input of the first decoder, the first and second groups in strokes which are connected to per-, Vym control inputs respectively series-parallel and parallel-serial converters, the second control input which is connected to the output synchronization unit load, which is connected to sinhrovyhod. the sync inputs of the second multiplexer, the first and second register, the first decoder, serial-parallel and parallel-serial converters, the transmission of commands and the interface block, addressable by the address inputs of the command block, the command transmission block, the information input of the second multiplexer and the information input of the second decoder, the first and the second control input of which is connected to the read and write outputs of the interface unit, and the outputs of the second decoder are connected respectively to the first and second control yuschimi input instruction receiving unit, the control input of the transmission unit commands and the first input of AND gate whose output is connected to the control input of the storage compounds, information output of which is connected to the data input of the second register, whose output is connected to second data input of the first multiplexer, informational ¹ ny the input-output of the speech memory is connected to the output of the first register, the information input of the buffer register and the information input of the command receiving unit, the information output of which is connected to and the information input-output of the interface unit, the information inputs of the memory of connections of the ith command transmission unit, the control unit of the command reception unit, the output unit of which is connected to the reception of the second recording cycles, i.e. provides switching of any input path to any output path in accordance with the information recorded in memory 8. The multiplexer 24 provides the transmission of the address for memory 8. Element And 25 generates a write pulse to memory 7 at the time of the tact TK (signal The above shows the process of passing information in switching mode. In this mode, blocks 26 and 27 do not take part, however, at the inputs 1 of the device, in various time channels 15 channels and various ports simultaneously come along with voice information commands for controlling the process of switching: commands. Choice of path or command disconnect. At the same time, information is received in the corresponding cycles in the unit 26 for receiving commands. If the input path is activated (the switch control command has arrived), all of the following information is transferred to memory 7, including the following switch control commands for other switches. Activation of the input path is removed when the jq decoupling of the disconnect command. If the processor has written a confirmation command to the command transfer unit 27, then simultaneously 1. It will be written to memory 62 (output command pointer). When reading 1 ”from the output of memory 62, it will be written to trigger 68” 1 which causes register 21 to be in tact TK, and register 69 is open, passing information to bus 28. Register 21 is opened only when “0” is read from memory 62, and 1 is read from one of the bits in memory 8, which determines the fact of path termination, if: the path is not turned off (on the output of the register 22 connected to the element And 65 - ”0”), the register 21 is closed. In this case, information is recorded in converter 6, which is defined as a disconnect command (all bits are well- ^{> and} left). This provides automatic path separation by all switching field switches. Command reception mode. The function of allocating commands is performed by the decoder 51. It distinguishes two types of commands: the shutdown control command and the disconnect command. In the initial state, disconnect commands are sent to all input ports (zeros in all bits of a 16-bit word). Decoder 51 generates a pulse at the first output. The write pulse from the output of the And 55 element to the input of the memory record. 48 passes only in tact T1 (signal 31). Thus, the incoming disconnect commands clear the memory 48 if it is written in any cells ”1. In preliminary read cycles of the memory 48, information from its output is recorded by a trigger 58, the output of which is connected to the input of the decoder 51. If this input is 1, then the disconnect command initiates a signal at the decoder output, if 0, then the signal at the second decoder output initiates shutdown control commands . During path activity, the decoder 51 does not respond to incoming control commands and responds to disconnect commands, and in the inactive state of the input path, the decoder 51 does not respond to disconnect commands and responds to control commands received along this path. This ensures that only those commands that the switch should respond to, or rather, the processor that controls the switch, are selected. Other ..... commands pass into memory 7.. \ Having found the command, the combination of blocks 51, 55, 56 generates recording pulses arriving at the memory recording inputs 48-49 and through element OR 57 and decoder 52 to one of the memory recording entries 50 of the input command pointer, where ”1, signaling received in memory of 49 teams. Having read information from the memory 50 through block 10, the processor knows about several commands received at once. The address at which the commands arrived in memory 49 is determined by the combination of the address at which memory 50 was read and the number of the bit in which 1 ”was written. Further, the processor at this address can read the command from memory 49 and execute it. The result of the execution should be expressed in a record in the memory of 8 connections of the corresponding information: either the path is switched off with a certain switching, or the path is turned off. At the same time eleven 1389011 12 whose output is connected to the control input of the buffer register, the control output of the second register is connected to the enable input of the command transmission unit, the first clock output of the $ synchronization unit is connected to the first clock inputs of the command reception and transmission units and the clock input of speech memory, the second clock output is 6ποηθ ka synchronization is connected to the second clock input of the command receiving unit, the third clock output of the synchronization unit is connected to the third clock input of the command receiving unit, the second clock input of the transmission unit commands * ³ and the second input of the AND, and a memory address input connections coupled to the output of the second multiplexer. 2. The switch by π. 1, wherein the instruction receiving unit comprises a memory of input commands; activity memory of input paths, memory of pointers, two registers, two multiplexers, two de-25 encoders, a trigger, two OR elements, three AND elements, the information input of the unit being connected to the information inputs of the input command memory and the first decoder, the outputs of which are connected with the information input of the memory of the activity of the input paths and the inputs of the first OR element, the output of which and the first clock input of the block through the first element AND are connected to the control inputs 35 of the memory of the input commands, the memory of the activity of the input paths and the first input of the second OR element, the output of which is connected to the control input of the second decoder, the output of which 40 is connected to the information input of the pointer memory, the output of which is connected to the information input of the first register, the outputs of which and the second register are connected to the information output of the block, the first address the input of which is connected to the first information input of the first multiplexer and the information input of the second multiplexer, the output of which 50 is connected to the address input of the input path activity memory, into the output of which ^{2 is} connected to the input of the trigger, the output of which is connected to the control input of the first decoder, the clock-55 input of the block is connected to the clock inputs of the first and 'second multiplexers, trigger and pointer memory, the second address input of the block is connected to the second information input of the first multiplexer, the output of which is connected to the information input of the second decoder and the address inputs of the memory of pointers and memory of input commands, the output of which is connected to the information. input of the second register, the first control input of the block is connected to the first input of the second element And and the first control input of the second register, the second control input of the block is connected to the first input of the third element And and the first control input of the first register, the second clock input of the block is connected to the second input of the third element And, the output of which is connected to the second control input of the first register, the third clock input of the block is connected to the second input of the second element And, the output of which is connected to the second control input of the second of the second register and the second input of the second OR element. 3. The switch according to claim ^, characterized in that the command transmission unit comprises an output command memory, a pointer memory, a trigger, a multiplexer, a register, an OR element, three AND elements, the information input of the block being connected to the information input of the output command memory, the output of which is connected through the register with the information output of the block, the first and second address inputs of which are connected via the multiplexer to the address inputs of the memory of the output commands to the memory of the pointers, the sync input of which is connected to the sync input of the block and the sync input multip The exhora, the control and the first clock inputs of the block through the first AND element are connected to the control input of the memory of the output commands and the first input of the OR element, the output of which is connected to the control input of the pointer memory, the output of which is connected to the first input of the trigger, the outputs of which are connected to the first inputs, respectively, of the second and the third elements And, the second clock input of the block is connected to the second input of the trigger and the second inputs of the second and third elements And, the input permission is connected to the third input of the third element And, the output otorrhea connected to the control output unit, an output of the second AND element is connected to the control input of the register and a second input element / OR ment.