SU1272336A2 - Device for connecting input-output devices from multisegment bus - Google Patents

Abstract

The invention can be applied in teleprocessing systems and computer networks built on the basis of the technical means of the Unified Computer System for the exchange of information between subscribers and the electronic computer, or between electronic computers over data transmission channels, and is complementary to the author. N 1226479. The purpose of the invention is to increase the utilization rate of equipment. The goal is achieved by the addition of a memory, a communication unit with a memory, a unit for switching channels of a computer to the device. 2 з.п, ф-л, 4 Il. (L

Description

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Go The invention relates to computing and can be applied in teleprocessing systems and computer networks based on the technical means of the Unified Computer System for the exchange of information between subscribers and an electronic computer or between electronic computers over data transmission channels. The purpose of the invention is to increase the utilization rate of the equipment. FIG. 1 shows a diagram of the device; in fig. 2 is a diagram of a computer switching unit; in fig. 3 is a block diagram of a memory communication unit; in fig. 4 is a diagram of a communication unit. The device comprises an address and data processing unit 1, a memory 2, a next address register 3, an address register 4, a communication unit 5, a data channel scanning unit 6, a display unit 7, a communication unit 8 with a display unit, a synchronization unit 9 connection with the display unit, control unit 10 and setting the exchange frequency, memory interface synchronization unit 11, bidirectional exchange switches 12, linear adapters 13, computer channel switching unit 14, memory communication unit 15, additional memory 16, outputs 17 and inputs 18 of these linear adapters, out odes 1–9 and input 20 of the device connected to the I / O channel of the first computer, output 21 and input 22 of the device connected to the input – output channel of the second computer. The channel switching unit (Fig. 2) contains composing fields 23 and 24, comparison circuits 25 and 26, elements ШШНЕ 27 and 28, elements AND 29 and 30, nodes of elements И31-34, triggers 35 and 36, element OR 37, enabling input 38 a control input 39, a control output 40, a communication unit with a memory (FIG. 3) holds the first shift register 41, the decoder 42, the buffer memory 43,: multiplexer 44, the second shift register 45, the control register 46 and state register 47, informational and equalizing input 48, address informational input 49; information control output 50, address information output 51. The communication unit (Fig. 4) contains the address register 52, the register 53 is the decoder 54, the control register 55, And 56, the buffer memory 57,. : IZH element node 58, command register 59, AND 60 node, control input 61, information control input 62, information input 63, control output 64, address output 65, information control output 66, information output 67. The interface of data transmission channels with a computer can function together with a computer in local and remote modes. In local mode, the device is logically connected to the I / O channel of the selected computer. When data is transferred from the computer, it goes through block 14 to block 5, from where it is written to memory 2. From memory 2, data is read by the program control and transferred to block 6 byte-by-bit. After transmitting the next data byte, block 6 causes discontinuous control programs by which the program The control reads the next data byte and transfers it to block 6, which performs parallel-serial data conversion and transfers them bit by bit through the switch 12 to the linear adapter 13, from where the data goes to the data transmission channel. When receiving data from the data transmission channel, the computer enters the computer in reverse order. If a computer fails during the data exchange, 1th unit 14 provides automatic switching to the backup computer, thereby significantly increasing the survivability of the system. Block 15 and additional memory 16 are not involved in the exchange of data between the computer and the data transmission channels. For the purpose of diagnostics, as well as in the event of a device failure, the unit 15 and the additional memory 16 provide for loading into the memory 2 internal functional tests stored on magnetic media. Performing internal functional tests allows you to check the operability of the device and in case of failure to localize the fault. In the remote mode, the device is located at a considerable distance from the computer and is connected via a data channel, which acts as a data concentration channel, with another device operating in the local mode. The data stream is described as follows. The device operating in the remote mode receives data from the data transmission channels and is recorded by the program control in memory 2. Next, the control program reads data from memory 2 and transmits them to the data concentration channel. From the data concentration channel, data is received by the device operating in local mode. and transmitted to the computer. The transmission from the computer is carried out in reverse order. Block 15 and additional memory 16 provide for loading of the device operating in the remote mode of the program, loading the control work program from the computer via the data concentration channel, as well as loading of the internal functional tests for diagnosing the device. Logical connection of the interface to the I / O channel of one computer is made when the trigger 35 is installed. Logical connection of the interface device to the I / O channel of the other computer is done when the trigger 36 is installed. The interface device is configured so that the device is not simultaneously connected to two computers. The connection to the channel was made by comparing the address coming from the I / O channel of the computer. and addresses received from the keypad 23 and 24 under the computer I / O channel. Disconnection from the channel occurs when the signal is received. The system is reset to the input of the flip-flops 35 and 36, as well as when the I / O channel is disconnected at block 7. The recording and control of the drive comes from block 1 to input 48 of block 15 and using output commands recognized the decoder 42 is recorded in register 41 and in register 46. From the output of the register 46, the signals controlling memory 16 are sent to the output 51 of the block 15. From the output of the register 41, the recording data in the serial code is also received to the output 51 of the block for recording on the media information and writing Entering the Buffer Memory 43. Data read in a sequential code from the information carrier is received from the input 49 of the block to the register 45 through multiplexer 44 using input commands recognized by the decoder 42, is received in parallel code to block 1 through the output 50 of the block 15. The commands in the control register 46 can set the diagnostic mode. In this case, the read data is transferred to the shift register 45 from the memory 43 through the multiplexer 44. In this case, the control program can write data to the memory 43, read the data and compare the read data and the write data, i.e. The operability of the block 15 can be checked without using the memory 16. The status data of the memory 16 is fed to the input 49 of the block 15, entered into the state register 47 and using input commands is fed to the output 50 of the block and block 1. The control data memory 16 from control register 46 is received at output 51 of the block and controls the operation of memory 16. The exchange of data between the computer and the device takes place via computer I / O commands, which are received in block 5 and through input 61 to the command register 59. The I / O command code through output 66 is outputted to block 1. The control program determines the mode of data exchange and, via input 62, issues a sequence of input and output commands that are decrypted on the decoder 54 and determine the further operation of block 5. When transmitting data from a computer, data received through the input 61 and the node 58 are stored in the buffer memory 57. From the buffer memory 57, the data through the output 67 is stored in the memory 2 at the address recorded in the register 52 of the address of block 3 on the output command. When transmitting data from the interface to the computer, the data from the memory is recorded in the buffer memory 57 via the output 64 and sent to the computer. The data exchange is carried out under the control of the control program. The information on the state of the device and the interface control from block 1, by means of output commands, is entered in the state register 3 and the control register 55. obsessed registers 53 and 55 through the output 64 enters the computer. With the help of the water and output diagnostic commands from the BCU, through element 56 and node 60, it is possible to check the interaction with the input / output channel of the local interface without connecting to the VM. Formula 1 and 1. Device for connecting I / O devices to a multi-segment highway according to aut. St. No. 1226479, characterized in that, in order to increase the utilization rate of the device, an additional memory, a computer channel switching unit and a memory communication unit are inserted into it, and the information input and output of the address and data processing unit are connected respectively with information and control output and input of communication unit with memory, address informational output and information input of which are connected respectively with input and output of additional memory, address output of communication unit is connected with second information The input of the address register, the information input and output of the communication unit are connected respectively to the output and the information input of the memory, the control input and output of the communication unit are connected to the control output and input of the computer switching unit, the input permit of which is connected to the information and indicator output of the communication unit with the display unit, the first input and output of the computer channel switching unit are connected to the bidirectional communication bus of the first computer, the second input and output of the computer channel switching unit are connected to the bidirectional other connection of the second computer, the channel switching unit of the computer contains two set fields, two comparison circuits, two triggers, two elements OR NOT, four nodes of elements AND, a node of elements OR, two elements AND, and the enabling input of the block is connected to the first inputs of the first and second elements OR NOT, the outputs of which through the first and second elements AND respectively are connected with single inputs of the first and second triggers respectively, the first input of the block is connected to the first inputs of the first node of the AND elements and the first comparison circuit and the null one by the entrance the first trigger, the output of which is connected to the first input of the second node of the elements AND, with the second inputs of the second element OR NOT and the first node of the elements AND whose output through the node of the elements OR is connected to the control output of the block. 36, the control input of which is connected to the first input of the third node of the elements AND and the second input of the second node of the elements AND whose output is connected to the first output of the unit, the second input of which is connected to the first inputs of the second comparison circuit, the fourth node of the elements And and the single input of the second trigger, the output of which is connected to the second inputs of the first element OR-NOT, the third and fourth nodes of the elements AND, the outputs of the first and second dialed fields are connected to the second inputs of the first and second comparison circuits, outputs cat ryh connected to inputs of the first and second AND gates, the outputs of the third and fourth nodes of AND gates respectively connected to the second output unit and the input element or assembly. 2. The device according to claim 1, wherein the memory communication unit comprises two shift registers, a control register, a status register, a decoder, a buffer memory, a multiplexer, the information and control input of the block being connected to the input of the decoder and the information inputs of the control register and the first shift register, the output of which is connected via a buffer memory to the first information input of the multiplexer, the output of which is connected to the information output of the second shift register, the outputs of the decoder are connected to the control the inputs of the first and second shift registers, the control register and the status register, the first output of the control register is connected to the multiplexer control input, the output of the first shift register and the second output of the control register are connected to the address information output of the block, the information input of which is connected to the second information input the multiplexer and the information input of the status register, the output of which and the output of the second shift register are connected to the information control output of the block. 3. The device according to claim 1, it is cast that the linking block contains the address register, the soscommand register, the buffer memory, the node of elements I, the node of elements ШШ, decipher 71

a torus, an element, and the information control input of the block is connected to the first inputs of the address register, the status register, the control register, the AND element, the buffer memory and through the decoder to the second inputs of the AND element, the address register, the state register, the control register the buffer memory and the first input of the node of the elements AND, the output of the element AND through the node of the elements OR are connected to the input of the command register and the third input of the buffer memory, the fourth input of which (the swarm is connected to the information input of the block, whose information output ene with the first exit buffer

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memory, the second output of which and the first outputs of the status and control registers are connected to the control output of the block and the second input of the node 5 of the elements I, the output of which, the output of the command register, the third output of the buffer memory and the second outputs of the control and state registers are connected to the information and control output 10 of the block, the control input of which is connected to the input of the node of the OR elements, the output of the address register and the third output of the control register are connected to the address output of the Vlock and the fifth input of the buffer memory respectively.

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Claims (4)

The claims which control input is connected to 1. A device for connecting input-output devices to a multi-segment highway according to ed. St. $ No. 1226479, characterized in that, in order to increase the utilization rate of the device, additional memory is introduced into it, a computer channel switching unit and a communication unit with memory, moreover, information-control input and output of the address and data processing unit are connected respectively to information controlling the output and input of the memory communication unit 15, the address information output and the information input of which are connected respectively to the input and output of the additional memory, the address output of the communication unit 20 is connected to the second information by the ionic input of the address register, the information input and output of the communication unit are connected respectively to the output and information input of the memory, the control 25 input and output of the communication unit are connected to the control output and the input of the channel switching unit of the computer, the permitting input of which is connected to the information and indicator output of the node 3θ of communication with the display unit, the first input and output of the computer channel switching unit are connected to the bi-directional communication bus of the first computer, the second input and output of the computer channel switching unit communication bus of the second computer, the channel switching unit of the computer contains two typesetting fields, two comparison circuits, two triggers, two elements OR-HE, four nodes of the AND element, · an OR element node, two AND elements, and the block allowing input is connected with the first inputs of the first and second elements OR-HE, the outputs of which through respectively the first and second elements AND are connected to the unit inputs of the first and second triggers respectively, the first input of the block is connected to the first inputs of the first node of the elements ₅₀ and And the first comparison schemes and null swing first flip-flop, whose output is connected to a first input of the second assembly of AND gates, with the second inputs of second OR-HE and the first assembly of AND gates, the output of which through the element or node is connected to the control output unit. the first input of the third node of the And elements and the second input of the second node of the And elements, the output of which is connected to the first output of the block, the second input of which is connected to the first inputs of the second comparison circuit, the fourth node of the And elements and the single input of the second trigger, the output of which is connected to the second inputs of the first OR-HE element, third and fourth nodes of AND elements, the outputs of the first and second typesetting fields are connected to the second inputs of the first and second comparison circuits, respectively, the outputs of which are connected to the inputs respectively the first and second AND elements, the outputs of the third and fourth nodes of the AND elements are connected respectively to the second output of the block and the input of the OR element node. 2. The device according to claim 1, characterized in that the communication unit with the memory contains two. a shift register, a control register, a status register, a decoder, a buffer memory, a multiplexer, wherein the information-control input of the unit is connected to the decoder input and the information inputs of a control register and a first shift register, the output of which is connected through a buffer memory to the first information input of the multiplexer, the output of which connected to the information output of the second shift register, the outputs of the decoder are connected to the control inputs of the first and second shift registers, control register and register On the other hand, the first output of the control register is connected to the control input of the multiplexer, the output of the first shift register and the second output of the control register are connected to the address-information output of the unit, the information input of which is connected to the second information input of the multiplexer and the information input of the status register, the output of which is the output of the second register shear connected to the information control output of the block. 3. The device according to claim 1, characterized in that the communication unit contains an address register, a status register, a control register, an instruction register, a buffer memory, an AND element node, an OR element node, a decryption unit 7 1272336 torus, element And, moreover, the information-control input of the unit is connected to the first inputs of the address register, status register, control register, element And, buffer memory and 5 through a decoder - with the second inputs of the element And, address register, status register, control register, buffer memory and the first input of the AND element node, the output of the AND element through 10 the OR element node is connected to the input of the instruction register and the third input of the buffer memory, the fourth input of which is connected to the information input of the block, the information output of which 5 is connected to the first output of the buffer memory, the second output of which and the first outputs of the status and control registers are connected to the control output of the unit and the second input of the AND element node, whose output, the output of the command register, the third output of the buffer memory and the second outputs of the control and status registers are connected to information and control output of the unit, the control input of which is connected to the input of the OR element node, the output of the address register and the third output of the control register are connected to the address output of the 8lock and the fifth input, respectively th buffer memory. 14 ggt 19 20 21 22 Figure 1 FIG. 2 FIG. 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