JPS6133489B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a communication control device for a data processing system. In particular, the present invention relates to a synchronous line connection of a communication control device, and relates to a half-duplex synchronous line connection device that is used by switching between a reception mode and a transmission mode.

The object of the present invention is to provide an efficient half-duplex synchronous line connection device which is a synchronous interface conforming to the Recommendation It is about supplying.

Synchronous interfaces that comply with the CCITT recommendation X series are T line (transmission line), R line (reception line),
C line (control line), I line (indication line)
In addition to simply transmitting and receiving data, the T and R lines are used in conjunction with the C image and I line to perform call origination, call reception, disconnection, recovery, etc. It also serves as a display.

FIG. 6 shows a time chart of a normal sequence (address call) from call origination to communication enablement in a DDX line-switched synchronous X series interface. A detailed explanation of this time chart is provided in the technical reference material ``Circuit Switching Service Interface'' published by Nippon Telegraph and Telephone Public Corporation.

In order to enable such control operations, in addition to transmitting and receiving data, there is also a function to directly control the T line, and a function to directly control the C line.
It is necessary to have the function of directly controlling the line and the function of monitoring control operations received by the R line and I line. In the present invention, the T line can be controlled in the reception mode, the R line and the I line can be monitored to detect and report disconnection or recovery operations, and the status of the R line and the I line itself can be read. Moreover, by configuring the C line so that it can be directly controlled, control operations on the line side can be detected.

Embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram of the entire communication control device according to an embodiment of the present invention. The communication control device includes a plurality of line connection units 10, a control unit 11 that controls these, and line termination devices 12 each connected to the line connection units 10.

FIG. 2 is a block diagram showing the configuration of the line connection section. The line connection section 10 is a bidirectional data bus 10
0, line connection selection line 101, register selection line 1
02, and is connected to the control unit 11 through an interrupt signal line 103, a write signal line 104, and a read signal line 105.
It is also connected to the line termination device 12 by a T line 110, an R line 111, a C line 112, an I line 113, and an S line 114. Although only one data line is shown in FIG. 2, it actually has the necessary number of bits.

The bidirectional data bus is connected to a control register 30, a parameter register 31, a data register 32, a status register 33, and an X register 34, each register being connected to a bidirectional data bus 100 via a multiplexer 35. . Furthermore, the data register 32 is connected to the serial/parallel conversion control circuit 3.
The serial/parallel conversion control circuit 36 is connected to the synchronous character detection circuit 40, the transmission control circuit 37, the supervisory control circuit 38, and the S line from the line termination device 12. Furthermore, the supervisory control circuit 38 receives the R line 111 and I line 1 from the line termination device 12.
13 and S line 114 are connected, and also connected to the X register 34. X register 34
is connected to the line termination device 12 via the C line 112. Further, the control register 30 and the X register 34 are connected to a transmission control circuit 37.

Therefore, the operation of each part will be described.

The control register 30 specifies the operating mode of the line connection unit 10, such as reception mode or transmission mode. The data register 32 stores transmitted data when in receive mode, and stores received data when in receive mode. The X register 30 stores control information, that is, control to set the T line to 0 or 1, on/off control of the C line, recovery request instructions, or the status of the I line, R line, disconnection interrupt line, and recovery completion interrupt line. do. This X register 30 is controlled in the receive mode and is not intentionally controlled in the transmit mode. Note that the control information here refers to control for setting the T line to 0 or 1, C
This refers to information that controls line on/off control and restoration request instructions. The multiplexer 35 has a function of selecting which register to read when reading the contents of each register.

Output lines from the control register 30 and the X register 34 are input to a transmission control circuit 37. Further, each register, that is, the control register 30, parameter register 31, data register 32, status register 33, and X register 34, is selected by the register selection line 102, and the write signal line 10
4 writes data on the bidirectional data bus 100, is selected by the register selection signal line 102, and is read out to the bidirectional data bus 100 via the multiplexer 35 by the read signal line 105. There is.

When exchanging data with each register, in the case of reading, the control unit 11 selects a designated register in advance via the selection line 102. For example, when the X register 34 is selected, the multiplexer 35 selects the data line of the X register 34,
The contents (data) of the X register 34 are output to the bidirectional data bus 100. This output timing is given by read signal line 105.

Next, in the case of writing, the control unit 11 similarly selects a designated register in advance via the selection line 102. For example, when the data register 32 is selected, data from the control unit 11 is input to the data register 32 via the bidirectional data bus 100. This input timing is given by write signal line 104.

In normal transmission, transmission data is written character by character into the data register 32, converted into serial bits by the serial/parallel conversion control circuit 36, and sent to the transmission control circuit 3.
7 to the line termination device 12 via the T line 110 in synchronization with the S line 114. The received data passes from the line termination device 12 to the R line 111 through the monitoring circuit 38, and after the synchronous character detection circuit 40 detects synchronous characters twice in succession, it is input to the serial/parallel conversion control circuit 36, where it is assembled into one character. and sent to the data register for reading. When transmission data is sent from the data register 32 to the serial/parallel conversion control circuit 36 or when received data is sent to the serial/parallel conversion control circuit 3
6 to the data register 32, an interrupt signal is generated on the interrupt signal line 103, and the control unit 11
gives the timing of data transfer.

The C line 112 can output an arbitrary value from the X register 34, and the I line 113 is input to the X register 34. The S line 114 is a timing signal sent from the line termination device 12 and is input to the serial/parallel conversion control circuit 36 and the monitoring circuit 38.

FIG. 3 is a diagram showing an example of the configuration of the transmission control circuit 37 inside the line connection section 10. This configuration is the first feature of the present invention. The T control line 41 is the output of the X register 34, and the reception mode line 42 and fixed value sending instruction line 43 are the outputs of the control register 30. These are each controlled by the control unit 1 as described above.
It has a logical value written from 1. Note that these lines are connected via formware, so
In the block diagram of FIG. 2, individual connection lines are omitted.

The operation of the device configured in this way will be explained.

First, in the case of reception mode, the reception mode line 42
loads the value "1" from the control section 11, and the flip-flop 50 is set. The output of this flip-flop 50 is supplied on the one hand to an inverter 55, which output is supplied to gates 53 and 5.
Close 4. This output is also supplied to the gate 52, which opens the gate 52 and leads the T control line 41 to the line. That is, by writing an arbitrary value from the control section 11 to the bit position corresponding to the T control line 41 of the X register 34, the T line on the line can be controlled.

In the case of the transmit mode, the receive mode line 42 is loaded with a value of "0" from the control section 11, and the flip-flop 50 is reset. In this case, gate 52 is closed and gates 53 and 54 are opened. When changing from the reception mode to the transmission mode, the fixed value transmission instruction line 43 is loaded with a value of "1" from the control section 11, the flip-flop 51 is set, the gate 53 is opened, and the output line of bit 7 of the data register 32 is set. 44 is routed onto the line. This operation is necessary to keep the T line in the marked state during the transition period from when it enters the transmit mode until when actual data is sent onto the line. It is necessary to write from the control unit 11. When it is ready to send actual data onto the line, the control unit 11 writes the data into the data register 32 and sets the fixed value sending instruction line 43 to "0". flip flop 51
is reset, gate 54 is opened, and data line 45, which is the output of serial/parallel conversion control circuit 36, is guided onto the line.

The state of T-ray control in such an operation is shown in the time chart of FIG.

Next, FIG. 5 shows an example of the configuration of the monitoring circuit 38.
This configuration is the second feature of the present invention. The recovery request line 61 is the output of the X register 34, and any value can be written therein from the control section 11. The S line 114 is connected to the I line 11 when the recovery request line 61 is "0".
3 is off and the R line 111 is "0" for more than 16 bit times, the disconnection interrupt line 62 is set to "1" and the serial/parallel conversion control circuit 3
This is the clock to 6. The recovery request line 61 passes through the inverter 74, and the I line 113 passes through the inverter 73.
The R line 111 is led directly to the AND gate 71 through the gate.

When the input conditions of the AND gate 71 are satisfied, a monitoring state is entered through the S line 114, and when the 16 bit time or more is reached, the disconnection interrupt line 62 is set to "1" and the control section 11 is notified of this. I line 1 on the way
13 from off to on, or when the R line 111 returns from "0" to "1", the disconnection recovery monitoring circuit 7
0 is initialized. The control unit 11 connects the cutting interrupt line 6
When detecting that 2 is "1", the disconnection line 6
2 to “0”, T line 110 to “0”, C line 11
2 is turned off, the recovery request line 61 is set to ``1'', and the recovery is completed. The I line 113 passes through the inverter 73, and the recovery request line 61 passes directly to the AND gate 72.
guided by. When the AND gate 72 is open, that is, when the recovery request line 61 is “1” and the I line 113 is “0”, when the R line 111 changes from “0” to “1”, the recovery completion The input line 63 is set to "1" and the control unit 11 is notified of this. When the control unit 11 detects that the restoration completion interrupt line 63 is “1”, it sets the restoration request line 61 to “0”.
Then, the restoration completion interrupt line 63 is set to "0" to know that the restoration is complete. Due to the above, the control unit 11
Recognize when a communication line is logically disconnected or restored.

At the same time, the R line 111 passes through the inverter 75.
The I line 113 is directly guided to the X register 34 and read out to the control section 11. Further, when receiving data, the R line 111 and the S line 114 are led to a serial/parallel conversion control circuit 36 in order to assemble the signals into characters. Such an operation makes it possible to monitor the R line 111 and the I line 113 as shown in the time chart shown in FIG.

Although we have explained one line connection part above, in the case of full-duplex system where transmission and reception are performed simultaneously, two
one line connection
line, C line and S line, and R line, I line and S line to the other line connection part.

As explained above, the overall operation is determined by the register write value, and in particular, control information is written to and read from the X register, and necessary information is read out via the register, so the control information transmission and reception of the control unit is This is done independently of line synchronization. Therefore,
A line connection unit that can be efficiently controlled by a microprogram can be provided. This results in
An efficient synchronization interface for the CCITT Recommendation X series is obtained.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the overall configuration of a communication control device according to an embodiment of the present invention. FIG. 2 is a block diagram showing the configuration of the line connection section. FIG. 3 is a circuit diagram of the transmission control section in the line connection section. FIG. 4 is an example of a time chart showing line interface, disconnection, and recovery operations. FIG. 5 is a circuit diagram of the monitoring section in the line connection section.
Figure 6 is a time chart of the normal sequence state of the synchronous X interface. 10... Line connection section, 11... Control section, 12...
... Line termination device, 100 ... Bidirectional data bus, 101 ... Line connection section selection line, 102 ... Register selection line, 103 ... Interrupt signal line, 104 ...
...Write signal line, 105...Read signal line, 110...
...T line, 111...R line, 112...C line, 11
3...I line, 114...S line, 30...control register, 31...parameter register, 32...data register, 33...status register, 3
4...X register, 35...Multiplexer, 3
6... Serial/parallel conversion control circuit, 37... Transmission control circuit, 38... Monitoring circuit, 39... Line connection control circuit, 40... Synchronous character detection circuit, 41... T control line, 42... Reception Mode line, 43...Fixed value sending instruction line, 44...Data register bits 7, 4
5... Data line, 50, 51... Flip-flop, 52, 53, 54... NAND gate, 55,
56...Inverter, 57...Driver, 61...
...Recovery request line, 62...Disconnection interrupt line, 63...Recovery completion interrupt line, 70...Disconnection recovery monitoring circuit, 7
1, 72...and gate, 73, 74, 75...
...Inverter, 76...Receiver.

Claims (1)

[Claims] 1. A data register capable of reading and writing, and a serial-to-parallel conversion control circuit for serial-to-parallel conversion of transmitted and received data, which is provided in the read and write data path of this data register and performs serial-to-parallel conversion of transmitted and received data. In a synchronous line connection device, there is an A transmission control circuit that sends the output data of the data register and the output data of the serial/parallel conversion circuit to this transmission line in the transmission mode, and this reception line connected to the reception line (R line) maintains space polarity for a certain period of time. 1. A synchronous line connection device comprising: a monitoring circuit that detects that a control line from an opposite device is in an OFF state, and generates a disconnection interrupt and a recovery completion signal.