SU1234842A1 - Multichannel interface for linking using equipment with digital computer - Google Patents

Abstract

The invention relates to computing and can be used to receive information into an electronic computer through several asynchronous channels. The aim of the invention is to simplify the device. The device contains a group of channels for receiving messages, a group of elements AND, a block of two-address memory, an address decoder, a pulse generator, two OR elements, each message receiving channel contains a message storage unit, a switch that sends a trigger, a trigger, element I. 1 Il. to soy4 00 4 Yu

Description

I

The device relates to computing and can be used to receive information into an electronic computer through several asynchronous channels.

The purpose of the invention is to simplify the device.

The drawing shows a block diagram of the device.

The multichannel device for interfacing subscribers with a digital computer contains i-3 channels for receiving messages, each of which includes a message storage unit 4., inputs 5-7 of the device, switch 8, connect, And element 9, trigger 10, And 11 group of elements 12, a pulse generator 13, a block of 14 two-address memory, an address decoder 15, an address input 16, an OR element 17, an output 18 of a device, an OR element 19, an input 20 of readings.

The device works as follows.

When a message arrives at any input, for example, input 5, it is recorded in channel I message storage block 4. Trigger 10 generates a Readiness signal, which is fed to the input of the And 9 element, and a Ban signal, which is fed to the input of the And 1 and It blocks a pulse — a millet from the generator's output of 13 pulses into channel 2. When a pulse arrives from the generator's output 13, the element AND 9 generates a signal that sends a message from the message storage unit 4 through the switch 8 to the input of the element OR 17 Except addition signal with} Element 9's input is fed to the input of element OR 19, where a recording signal is generated in block 14 of the memory memory, and to zero input of trigger 10 where the Ready and Disable signals are reset by this signal. The decoder 15 addresses extracts from the information to the element ШИИ 17, the address that arrives at the second address input of the block 14 of the dual-address memory. At the same time, the information from the output of the element Iirni 17 to the address formed in the decoder 15 and the control signal of the record 9 in block 14 two-digits waist memory.

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The next impulse from the generator 13 output goes through the AND 11 element to interrogate the next channel 2. If the message in channel 2 is received in the message storage unit 4 and is ready for output (in the flip-flop 0, the Ready and Disable signals are generated), it is similarly described to block 14 bicast memory. If there are no messages in channel 2, then the signal from the output of the And 2 element goes to the next channel for polling. Thus, for each pulse of the generator 13, one message is rewritten from channels 1-3 to block 14 of the two-address memory, provided that such a message has arrived at least in one of the channels. If no new messages were received in channels 1-3, then the next pulse from the generator 3 output does not overwrite the message in block 4. In order to avoid loss of input messages, the pulse frequency of the generator 13 should be 5 such that in the minimum period of the messages following the inputs 5-7, the number of pulses, not less than the number of channels 1-3, was inserted. At the same time, the input messages received at the inputs 5-7 of the device and recorded in the message storage units 4 in the corresponding channels 1-3 are rewritten into the block 14 of the dual-address memory.

The contents of block 14 of the dual-address memory enter the digital computer via commands that are generated by the digital computer. To do this, the first address input 6 and the control input 20 are read in the address of the desired message and the impulse to match the corresponding. At the same time, a message appears at the information output, which arrives at the output 18 of the device and then into the digital computer.

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Claims (1)

Formula iso et e and A multi-device interface: subscribers with a digital computation maigan containing a group of message receiving channels, each of which contains a message storage unit, a switchboard, and the information inputs of the message storage units are connected to the information output of the HbD S subscribers messages the output of the message storage unit is connected to the information input of the ccg mutator 31 In order to simplify, a two-address memory block, an address decoder, two OR elements, a pulse generator, a group of AND elements are entered into it, and an AND element and a trigger are entered into each message reception panel. the output of the two-address memory block is connected to the information input of the digital computational interface, the first address input of the two-address memory block is connected to the address input of the digital computer, the input of the two-address memory block is connected to the read output a digital computer, the second address input of the two-address memory block is connected to the output of the address decoder, the input of which is connected to the output of the first OR element and the information input of the two-address memory block, whose recording input is connected to the output of the second OR element, the group of inputs of which is connected to the outputs elements and channels of reception 348424 group messages, the group of inputs of the first element OR is connected to the outputs of the switches of the contact channels of the group messages, the output of the pulse generator 5 is connected to the first input of the first element AND group and the first input of the element AND the first channel of reception of group messages, the output of the i-ro element AND group connected 10 with the first input (i + O ro of the AND group element and with the first input of the AND (i + l) element of the group receiving messages, the output of the last AND group element is connected to the first input-element of the AND last channel group messages, while in each channel receiving messages the input of the message storage unit is connected to a single trigger input, a single 20, the output of which is connected to the second input of the AND element, the output of which is connected to the control input of the read switch and the zero input of the trigger, the zero output of which is connected to the second input of the corresponding AND element of the group. 78 Compiled by S. Pestman Editor E, Konga Techred M. Khodanich Proofreader A.T. Order 2987/52 Circulation 671 Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, 4/5 Rautskisk nab. Production and printing company, Uzhgorod, st. Project, 4