SU1295408A1 - Device for accumulating and processing information - Google Patents

Abstract

The invention relates to the field of computer technology and can be used in digital information processing devices in various spectrometric systems, for example, to accumulate information in measurements of the amplitude or time spectrum. The purpose of the invention is to increase the speed. The device contains an operation unit 1, a switch 2 with a three-stable state, a memory block 3, an analog-digital converter 4, a generator of 5 clock pulses, a system controller 6, O F (L to Co 01 4: O 00

Description

I / O block 7, decoder 8, counter 9, elements AND 10-14, IDN element 15, trigger 16, one-shot 17, switch 18 with a three-stage state and trigger 19. The goal is achieved by organizing the device in the information accumulation mode, where, after receiving the end of data conversion signal, the information code is transferred to the counter, and the operation unit reads from the memory block into internal registers.

The invention relates to computing and can be used in digital information processing devices in various spectrometric systems, for example, to accumulate information when measuring amplitude or time spectra,

The purpose of the invention is to increase speed.

Figure 1 shows the functional diagram of the proposed device | FIGS. 2 and 3 are timing diagrams illustrating the operation of the device.

The device for storing and processing information includes an operation unit 1, a first switch 2 with a three-state condition, a memory unit 3, an analog-to-digital converter (ADC) 4, a clock generator 5, a system controller 6, an input-output unit 7, a decoder 8 , counter 9, third 10, first 11, second 12, fourth 13 and fifth 14 elements AND, element OR 15, first trigger 16, one-shot 17, second switch 18 with a three-stable state, second trigger 19, address output 20 operational block, output 21 of the first switch with three-stable state, address input 22 of the memory unit, output 23 of the sign of the end of the analog-to-digital converter conversion, single-vibrator output 24, counter output 25, output of the second switch of the three-state switch, outputs 27-29 of the decoder, outputs 30 and 31 setting the first triggers command - increase the contents of the memory cell by 1. Then the decoder locks the switch and the address of the information channel is output from the counter via the switch to the address input of the memory block. The operation unit executes the command, but with the data of the memory cell location indicated by the information channel address. To perform +1 operation, only one instruction is required per memory location. 3 il.

Pa, the output 32 of the recording control in the memory of the system controller, the output 33 of the second trigger, the output 34 of the first element And the output 35 of the second element 5 and And, the output 36 of the element OR, the output 37 of the third element And, the output 38 of the fifth element And, the output 39 the fourth element And, the bus 40 data and analog input 41. In figure 2 and 3, the numbering

 About diagrams corresponds to the output numbers of the device blocks.

The system controller is designed to form the control signals and interface with the operating unit, the memory and with the interface circuits, peripheral devices. The system controller can be implemented on the basis of КР 580ВК28. Operational unit 20 may be implemented based on

KR580IK80A. As a converter, for example, a time or amplitude coding unit may be used. As switches

25

2 and 18, you can use the scheme type K 589, Ap 16.

The device works as follows.

In order to accumulate information received from converter 4, for example, in memory block 3, an area is allocated. In this area, two cells are used for one information channel.

memory Preliminarily, an arbitrary address of the memory location is written to the registers of the operation unit, for example, in H and L, and

312

memory with addresses 0000 and 0001 — INRM commands — increase the contents of the memory cell addressed by registers H and L by 1. The conversion end signal from output 23 of converter 4 unlocks decoder 8, and sets counter 9 to output from single-vibrator output 24 by address 0000, triggers 16 and 19 are in state 1 and transfer digital information (address of the ADC information channel) jis converter 4 to counter 9. Trigger 19 unlocks the system controller 6. The operation unit starts executing the program from the command in block 3 memory in whose e with the address 0000. To execute the INRM command, the operating unit requires three machine cycles (K, K, M) or ten generator acts. In the cycle M, the zero address goes to address output 20 through switch 2 to the address input of the memory block and reads the command code into the internal registers of the operation unit. In the M and M cycles of J command execution, a pulse from output 27 of the decoder 8 blocks switch 2 and, via switch 18, sends to its output 26 the address from counter 9 to the address of the information channel of the ADC. The operating unit executes the INRM command, but with data from the memory cell addressable by the contents of the counter 9. If, after the execution of the specified command, this memory cell does not overflow, the pulse from the decoder code 28 goes to the And 11 element and its output 34 through the element OR 15 (output 36) to converter 4, set it to its initial state, and trigger 19 - to state O, whose output 33 blocks system controller 6. The device is ready to receive the following information from converter 4. If doing this coma As the cell of the memory block overflows, the device performs a transfer operation 1 to the second cell of the memory block of this information channel (FIG. 3). At the same time, at the output 38 of the element AND 14 a pulse appears, and the pulse at the output 39 of the element 13 and the trigger 16 translates into the state O and increases the content of the counter 9 by 1. The pulse, from the output 28 of the decoder 8 does not form a pulse at the output of the element AND 11, and consequently, at the output of the element OR 15. The operating unit is terminated084

It runs the first one and starts executing the command located in the cell with address 0001. To execute the specified command, address 0001 from the operation unit on output 20 goes through switch 2 to address input 22 of memory unit 3. The same INRM command is written to cell 0001 of the memory block. In the execution cycles, the operational block of this command performs operations similar to those indicated. But in mc and m, the pulse from the output 27 of the decoder 8 blocks the switch 2, and through the switch 18 transmits to the address input 22 of the memory block the address from the counter 9, which is greater by 1 of the previous address. An operation block executes an INRM command with data from this cell. Then the pulse from the output 29 of the decoder 8 goes to the element AND 12 and from its output through the element OR 15 to the converter 4, sets it to its initial state, and the trigger 19 - to the state O, the output 33 of which blocks the system controller 6. The device is ready to receive the following information.

Claims (1)

Invention Formula A device for accumulating and processing information, containing an analog-digital converter, an operational unit, an input / output unit, a system controller, a clock generator, a memory unit, and a first switch with a three-stage state, the first and second clock generator outputs being connected respectively, with the synchronous inputs of the operating unit and the system controller, the first information input / output of which is connected via an internal data bus to the input / output data of the input / output unit and the operating unit block whose address output is connected to the information input of the first switch with a three-state state, the output of which is connected to the address input of the memory block, the information input-output of which is connected via the internal system bus to the second information input-output of the system control, memory control output which is connected to the read write input of the memory unit, the output of the I / O feature, the output of the sign of the transition to a high resistance state and the output of the write attribute in the memory of the operation unit is connected respectively to the input of the I / O feature, the status control input of the outputs and the input sign of the memory write to the system controller, the output I / O control output which is connected to the input / output control input of the input / output unit the output, the information input-output of which is connected to the device data bus, the analog input of the device is connected to the information input of the analog-digital converter, characterized in that, in order to improve speed, it further comprises a one-shot, a decoder, five AND elements, an OR element, two triggers, a counter and a second switch with a three-stable state, the output of the conversion end of the analog-to-digital converter connected to the single-shot input and the gate input of the decoder, whose information input connected to the address output of the operating unit, the reset input of which is connected to the output of the one-shot, to the inputs of the installation in 1 of the first and second triggers and the input of the record counter Unified data output from the analog-digital converter, converting the condom control input coupled to an input YU 15 95A086 installation in O of the second trigger and with the output of the IZH element, the first and second inputs of which are connected to the outputs of the first and second elements, respectively, the first inputs of which are connected respectively to the first and second outputs of the decoder, the third output of the decoder is connected to the first input of the third element And and control inputs of the first and second three-state switches, the information input and the output of the second three-state switch are connected respectively to the output of the counter and the address input of the memory unit, the second input of the third element I is connected to the write control output to the memory of the system controller whose blocking input is connected to the output the second trigger, the input of the installation in About the first trigger connected to the counting input of the counter and the output of the fourth element And the first and second inputs of which are connected respectively to the outputs tr Another of the five elements I, whose input is connected via an internal system bus to the information input-output of the system controller, the second inputs of the first and second elements I are connected respectively to the direct and inverse outputs of the first trigger. 20 25 thirty FIG. 2 Editor I. Shulla Compiled by Y.Lantsov Tehred I.Popovich 619/56 Circulation 673 Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., d, 4/5 Production and printing company, Uzhgorod, ul, Proektna, 4 Proofreader N.Korol