SU1293734A1 - Device for entering analog information - Google Patents

Abstract

The invention relates to computing and measuring technology and can be used in automated monitoring and control systems, as well as in automation systems. scientific research. invention is the understanding of the accuracy of the device. The goal is achieved by introducing into the device the first and second counters, the EXCLUSIVE OR element, the NOT element, the second AND element, and the second OR element with corresponding links. The changes in the design make it possible to reduce the dynamic error in the conversion of input signals, the occurrence of a choke due to the presence of dead zones in the range of input signals in which the signal conversion is impossible. The device is controlled by a firmware control unit. 2 nl. l you with with "with 4

Description

The invention relates to computing and measurement technology and can be used in automated control and management systems, as well as in automation systems for scientific research.

The purpose of the invention is transformation accuracy.

FIG. 1 shows the block-removal device; in fig. 2 - temporary U diagrams.

The device contains information, address outputs 2, the first information group of outputs 3, 5, control output 4, control input 5, comparators block 6, first element OR 7, microprogram block 8

/ control, driver 9 signals, first counter 10, digital-analogue 20 converter (PAP) 11, block 12 elements And, register 13, second counter 14, first element And 15, trigger 16, second information group of outputs 17, second element OR 18, the element is NOT 19, the second element is AND 20 and the element is PERFUME OR 21.

The device works as follows.

In the initial state, the bits 30 of the counter 10 are in the unit one, and the counter 14 are in the zero state, which allows to eliminate the dead zones of the conversion range in which the input 35 cannot be converted.

signal (the input signal is converted only after the exit from the dead zone, which takes a certain time, the dynamic error increases accordingly, i.e., 40

conversion accuracy).

To the summing input of the second counter 14, which controls the higher bits of the D / A converter 11, block 8 supplies a pulse. A DAC 11 converts the code formed into an analog value, then sent to the input of the comparators of block 6, which compare this value with the analog value at inputs 1. If any of the input values is less than 50 than the signal at the output of the DAC 11, then the comparator is in the single state (the initial connection of the comparators is zero, so the PDA signal at the output of the D / A converter 11 is equal to 55 and less than any input signal), and the OR 7 element produces a signal

arriving at block 8. In this case, block B generates a signal arriving at the input. Setting the counter 10 and the unit input to zero triggers 16. At the same time, a unit potential is applied to the input of element 20 from the output of element 19. After this, block 8 generates a sequence of pulses arriving at the summing input of the counter 10 for controlling the lower bits of the D / A converter. When a single signal appears at the output of the element OR 7, block 8 prohibits the output of pulses to the input of the counter 10 and forms a request at the control input 4. At the same time, the signal conditioner 9 generates at its outputs the position and binary codes of the highest number of the comparator those that are currently in a single state. The signal at the control output 4 to the external device (not shown) and the binary code of the address at the address outputs 2 is carried out; the writing of the conversion result code from the outputs of the counters 10 and 14 to the outputs 3 and 17 of the device is recorded.

At the end of this operation, block 8 generates a signal that goes to the inputs of the elements And in block 12, This signal does not pass to the summing input of the counter 10 through the element 20 because there is zero potential at the other input of the element 20.

The content of the counter 10 remains unchanged. It remains unchanged even if the code is recorded from this counter multiple times. However, the possibility of the occurrence of errors is eliminated, i.e., the accuracy is increased.

The second VHO.SHY zlementov And in block 12 are connected respectively to the outputs of the imaging unit 9 signals, on which the position code of the address of the analog values is formed, for which the input analog value is equal to the analog value at the output of the DAC 11 ..

Therefore, in the presence of a signal on any of these outputs of the former 9, the corresponding trigger is set in the register 1 of the 13 in a single state. Since the signal from the outputs of the triggers re-. The horn 13 enters the inhibitory input of the corresponding comparator in block 6, it is forcibly set to the zero state and held there until the end of the entire conversion cycle.

If, at the same time, a single signal on the output of the element OR 7 is saved, which indicates the presence of a single state in one or more comparators, then block 8 generates the next signal to output information to an external device. This process continues as long as there is a single signal at the output of the element OR 7. When the signal at the output of the element OR 7 becomes zero, i.e. forcibly using the corresponding trigger register 13 is set to the zero state, the last of the comparators that have been triggered, block 8 generates a further sequence of pulses arriving at the input of the tOo counter

After the counter is installed in the unit state, a signal is generated at its output, which arrives at the zero input of the trigger 16 and sets it, respectively, into. zero state. The trigger 16 is set to the zero state only when the output of the element OR 7 has zero potential. If a single potential is present at the output of the element OR 7, then the signal at the output of the element EXCLUSIVE OR 21 does not appear until all the comparators in the single state have been set to the zero state.

According to the trigger signal 16, block 8 again generates a signal arriving at the summing input of counter 14. If, after increasing the content of counter 14, the signal at the output of LI element 7 remains in the zero state, block 8 generates another pulse arriving at the summing input of counter 1A . This continues until, after the next increase in the number of counters 14 at the output of the element OR 7, a single signal does not appear. When it appears, the sequence of operations described above is performed again.

The unit state of any of the triggers of register 13 is kept until the end of the conversion cycle, which ensures that, at the end of each act of conversion, the results of transformation are remembered only along those inputs 1,

3734

comparators of which are ustavar.piruts in a single state in a given conversion step.

The number of triggers in register 13 is equal to the number of comparators in block 6 and is therefore equal to the number of input variables 1. When the corresponding komparator is activated after the end of the conversion result recording

(code stored in the counters 14 and 10) at the address generated in block 9, each of the triggers in register 13 is set to one. If all the triggers of register 13 are set to one, as evidenced by the presence of a single signal at the output of the element And 15, then all input analog signals are already converted into two

The binary code and frx binary equivalents are stored in the corresponding memory cells and in the external device.

In this case, block 8 finishes the conversion cycle {and and produces

the signal that sets-up the counters 10 and 14, as well as the register 3 to the initial state. The generation of this signal can also be carried out before the start of the next conversion cycle.

In the device, the firmware control unit 8 performs the following functions: according to the signal at input 5, it forms the input H tnyjTbc arriving at the summing input of the counter 14; at the calicia of zero signals at the output of the element OR 7 and at the output of the trigger 16, it generates subsequent pulses arriving at the summing input of the counter 14; when there is a single signal

at the output of the element OR 7 and the zero signal at the output of the trigger 16 generates a pulse arriving at the input. Setting the counter to zero at zero, as well as a series of pulses arriving at

summing the input of the counter 10 and the input unit 12 elements And; at the presence of a single signal at the output of the elec- tant I 15, it forms a 1 pulse, indicating the end of the conversion, which goes simultaneously to output 4 and to the installation inputs to the initial state of the counter in 10 and 14, as well as register 13.

Block 8 can be implemented on

microprocessor set 580 according to standard computer systems ynpanjiamiunx, incl. flow of the block diagram elements - on the integral element base of the 155, 580 series, counters 10 and 14 - on four-bit binary reversible counters K155IE7. As an element EXCLUSIVE OR OR ispolzawa and chip K155LP5. i.e.

2 times more than

in the proposed device. When reading the next value of npi P niHocTb, the OR, AND, copies are NOT implemented on mic-5 even more:

those. accuracy decreases. In the proposed device (FIG. 2 g), the K155LAZ Prashroshseme.

Timing diagrams of the input signals and signals from the DAC of the prototype and the proposed device illustrate the transformation accuracy.

Introduction to the device of the first counter 10 with presetting its bits into a single state to control the lower bits of the D / A converter 11, AND 20, NOT 19, OR 18, and DEDUCTIVE OR 21 elements allows converting input signals across the entire conversion range. accuracy (dependent on quantization step S) for all values of input signals.

In the time diagram (Fig. 2a), the case is considered that the magnitude of the input signal falls into the dead zone - zone A, where the conversion is impossible. Reading this value occurs when the signal changes its destination, i.e. erroneous reading from another quantization step occurs. The conversion error in this case is (5.

Sh

{five

The accuracy of the conversion is unchanged during the reading process. It is equal to rS

4 The proposed device for inputting analog information has been developed for spectral and correlation analysis of turbulence fields.

Claims (1)

Invention Formula 20 An analog information input device containing a register, a digital-to-analog converter, a signal conditioner, an AND block, the first OR element, a first AND block, a microprogram control unit, a comparators block and a trigger, information inputs of the comparators block group, the first block input  firmware control, the outputs of the first group of the signal conditioner and the first output of the firmware control block are the information inputs of the device that control the device 35 output dead, the device address outputs and the control output of the device, respectively, the second output of the firmware control block is connected to the gate input 40 registers, the third exit - with the input of the block of elements And, the fourth exit of zones is not due to the preliminary setting of the digits counter to unit state and different control of counters in relation to the prototype unit 8. In this case, the conversion error  equal to the value, i.e. to the point with the setup input of 1 trigger, the output of the digital-to-analog converter is connected to the information input The value of the proposed device is increased by a minimum of 2 times (Fig. 2S). 45 block comparatorVd output which The time diagram of the operation is connected to the inputs of the signal generator (FIG. 2 &) and the first element OR is shown, the output is tea and one quantization step of which is connected to the second input of several input signals of the same firmware control block, howl In this case, at the time of 50 exits of the second group, the signals are connected to the inputs of group OR elements, the outputs of which are connected to the information inputs of the register, the outputs of which are connected to supplying the signal from the first output of the control unit to the input of the unit 12 elements I; And the contents of the counter 10 controlling the lower bits of the D / A converter are altered and when the second input is read to the 55 control inputs of the comparators block inaccuracy arises conversion result. Sin -.one measurement in this case i.e. 2 times more than The accuracy of the conversion is unchanged during the reading process. It is equal to rS 4 The proposed device for inputting analog information has been developed for spectral and correlation analysis of turbulence fields. Invention Formula Device for inputting analog information containing register, digital-analog converter, signal conditioner, AND block, first OR element, first AND block, microprogram control unit, comparators block and trigger, information inputs of the comparators block group, first input of the block of the firmware control, the outputs of the first group of the signal conditioner and the first output of the firmware control block are the information input of the installation in 1 trigger, the output of the digital-to-analog converter is connected to the information input ComparatorUd block output which and the inputs of the first element And, the output of which is connected to the third input of the firmware control unit, the fourth input of which is connected to the trigger output, characterized in that, in order to increase the accuracy of the device, the first and second counters, the EXCLUSIVE OR element, the NOT element, the second the element AND the second element OR, the outputs of the first and second counters are connected to the inputs of the digital-to-analog converter and are the information outputs of the device of the first and second groups, respectively, the second output of the microprogram control unit is connected to the first installation input of the first and the installation input of the second counter, the fourth output is the second installation input of the first counter, the fifth output with countable the input is the counter, the output of the first spike I.PI is connected to the first input of the EXCLUSIVE OR element and the first input of the second OR element, the overflow output of the first counter is connected to the second input of the second OR element, the output of which is connected to the second input of the ICR1CEE OR element, the output of which is connected with the output set to the O flip-flop, the output of the microprogram control unit is connected to the first input of the second element AND, the output of the first element OR is connected through the element NOT to the second input of the second element AND; the output of which is connected to the counting input of the first counter. fPuz.1 O g ft b to 10 12 16 id n / Nfnt) f a) tr 02 6 8 iO O 2 if 6 to 10 iZ Tacts b) but Input OeM  X / Signal with Zmh. ЦА1 O 2 b fff 8} 118. So you Input OeMiw bf  X / Tonty