SU1517044A1 - Device for optimizing multidimensional parametric series - Google Patents

Abstract

The invention relates to computing and can be used to solve problems of optimization of multidimensional parametric series. The purpose of the invention is to improve the accuracy of the device. The device provides an accurate solution for optimizing multidimensional parametric series. The device contains a control unit 4, a unit 1 production and operating costs, a unit 2 initial costs, a unit 3 adders. 1 il.

Description

cl

01

about

The invention relates to computing and can be used to fisiii task tasks. Optimization of multidimensional parametric series. These problems arise when it is necessary to determine the optimal set from the initial set {1 1, 2 ,,.,, Mn) of types of products with limited interchangeability. to meet the needs of a given set of their types 1, 2, ... ..., p.

Mathematically, one of the most common standardization problems — the task of optimizing multidimensional parametric series — is formulated as follows:

Define L I such that

f (c) (co) / a) / 41,.

Where

(s) С ° + X. minC, ..;

- je3 ieuJ

feuj o

WITH; - initial costs associated with the use of the i-ro type and not dependent on the number of these products; Cj- is the production and operational costs of satisfying the i-ro type of needs of the j-ro type. The purpose of the invention is to improve the accuracy of the device.

The functional diagram of the device is shown in the drawing.

The device comprises a unit 1 of production and operational costs, a unit 2 of initial costs, a unit 3 of adders, a block 4 of control,

The unit 1 of production and maintenance costs contains a matrix of 1 set of 1 I costs 5.;, i 1 m, j 1, n and shuntlly11 and 1 x resistors 6; j 1, p. The cost setting cells 5 are designed to set values C — production and operational costs, and each of them contains a key 7, a setpoint 8, a load resistor 9, and a diode 10.

Block 2 of the initial costs contains m cells assigning the initial costs P

,,,, w Kssda of which is designed to set the value of C,, i 1, m and contains the key 12 and the setting device 1 3,

The control unit 4 is designed to set the version of the products used (JS 1), to give the start signal

five

0

five

about

solutions, (determining the best variant o (S 1 and contains counter 14 analogue (; - digital converter 15, comparison circuit 16, triggers 17-19, registers 20 and 21, element 22 and element OR 23, delay elements 24 and 25, the device launch input 26, a banner 27.

The device implements an algorithm for solving the optimization problem for multidimensional parametric series, the essence of which lies in the sequential enumeration of all possible options AND the choice of the best one, i.e. allows you to find the exact solution to the problem.

The device works as follows.

Before the start of the decision, the supply buses are energized and set the 8 setpoint costs 5; , i 1, m, j 1, p are set to the voltage U- proportional to the values of С ,, production and operating costs, and the setting units of the 13 cells of the task of the initial expenses llj i- I, m are set to the direction proportional to the values of С ° initial costs.

In addition, the counter 14, the register 21 is zeroed, the maximum-possible binary number (111 ... 1) is written to the register 20, the triggers 17-19 are set to the state O.

The solution of the problem begins by applying a short pulse to the device start input (the duration of the pulse must be less than the delay time of the pulse in delay element 25). This pulse arrives at the first input of the ShSh 23 element, from the output of which the signal enters the input of the trigger setup 17, converting it to the state 1. From the trigger 17 output, the signal arrives at the input of the delay element 25, where it is delayed by the time required to calculate the value (s) in the block of adders, and on the counting input of the counter 14, the outputs of which form a binary on the combination 000 ... 01, i.e. option a is set; f includes only products of the first type.

From the outputs of counter 14, the binary combination 000 ... 01 goes to the inputs of register 21 and to the control inputs of blocks 1 and 2, the closure keys 7 of the first line of the cost setting cells 5, ...,

0

five

0

five

..., 5 ,, block 1 and key 12 cells ll block 2,

In unit 1 production and operating costs for each of j 1, n columns of task cells 5, -j, i 1, m load resistors 9, diodes of 10 cells of the column and resistor 6 form the minimum voltage selection circuit, the output of which is always maintained voltage equal to the minimum of the voltages at the reference points connected to the cells of the column, i.e. resistors 6: j 1, n will always maintain a voltage proportional to min C; -, j 1, n,

i € (J

 which goes to the first inputs of the block of adders, to the second inputs of which from the connected cells of the cost assignment will receive a voltage, the reference value of the values С, ieu).

In block 3 adders, the value is determined

Z

lELO

WITH

+ min, je j iew

which is fed to I1) d analog-to-digital converter 15.

After determining the value of f (u), the signal- delayed by the delay element 25 is fed to the reset input of the trigger 17, its transfer to the O state and to the installation input of the trigger 18, a single signal from the output of which is fed to the input of the delay element 24, where it is delayed for the time required to complete the comparison of numbers in the comparison circuit 16, to the control input of the analog-digital converter 15, from the output of which the number equal to f (w) is fed to the first input of the comparison circuit 16 and to the input of the register 20. At the same time, the signal from trigger output 18 will go on the first input of the element 22, the second input of which supports the signal of the logical unit, from the inverse output of the trigger 19, which also enters the read input of the register 20, ensuring the flow of the number f to the second input of the comparison circuit 16.

The signal from the output of the element K 22 is fed to the control input of the circuit 16

5Q Further, the whole described process is repeated many times until all possible combinations of the used products have been enumerated (at that, counter 14 each time changes its state by one and the total

compare, permitting compas

The number of f (ci;) and f numbers given for the number of combinations is 2). Pos10

enter the trigger setup input

19, putting it into state I. In this case, the signal from the inverse output of the flip-flop 19 becomes equal to 0, which closes the AND 22 element, not allowing the numbers to be compared, and prohibits the f from the register 20 from being compared to the reference device 16. Simultaneously, the signal from the output of the trigger 19 is fed to the input register entry

20, in which the new value f f (o)) is written, as well as to the input of the record of the register 21, in which it writes J5 with the combination, giving the best value of ffu)).

After performing these operations, the signal delayed in the delay element 24 is fed to the reset inputs 20 of the flip-flops 18 and 19, transferring them to the state O. The signal from the inverse output of the flip-flop 19 will permit the supply of a new number from the register 20 to the second input of the comparison circuit 16 and on

25 second entry element And 22, thus fixing the readiness to implement a new comparison of numbers.

In the event that f f (u)), then the signal at the output of the comparison circuit 16

30 is not present and the signal from the output of the delay element 24 will switch the trigger 18 to the state O, removing the control signal

35

40

From the analog-digital converter 15 and stopping the supply of the number f (co) to the comparator device 16 and the register 20. In the first and second cases, the signal from the output of the delay element 24 also goes to the second input of the element OR 23; 17 to state 1, the signal from the output of which enters the counting input of the counter 14, the outputs of which form a new combination 000 ... 10, which corresponds to the new

the use of products, and, at the same time, to the input of the element of the setting unit 25, ensuring the further operation of the device by analogy with that considered.

Further, the entire described process is repeated many times until all possible combinations of the used products are enumerated (the counter 14 each time changes its state by one and the total

his inputs.

If the condition f (uf) f is satisfied, then the signal from the output of the comparison circuit

Just how the last option 1 1 1 ... 1 1 is analyzed in the next step at the output of the counter 14 according to

an overflow signal that enters the transparency 27, signaling the end of the decision. At the same time, the registra 21 stores the optimal variant of the products used (o ("1)" and in register 20, the value of the minimum costs (f (o)) corresponding to this variant.

In this case, the problem is solved exactly, because all possible combinations of products are viewed.

At the same time, the time to solve the dimension problem (the HRP can be estimated as t resh 2 (-U + 1)), where f, C 7. the delay time in delay elements 24 and 25, i.e. does not depend on the value of n, which is essential for problems of large dimension-.

Claims (1)

Invention Formula A device for optimizing multidimensional parametric series, containing a unit of production and operating costs, a block of adders and a control unit, characterized in that, in order to improve the accuracy of the Device / - control unit, the device contains digital converter, first, second and third triggers, first and second registers, first and second delay elements, AND element, OR element, counter and transparency, the first output of which is grounded, the second output is connected to the overflow output counter the output of which is bitwise combined with the information input of the second register and is -40 with the output of the control unit, the counting input of the counter is connected to the output of the first trigger and the input of the second delay element, the output of which is connected to the reset input of the first trigger the output of which is connected to the input of the first delay element, the first input of the element I and with the control input of the analog-digital converter, whose information input is the information input of the control unit, and turn is connected to a first input of a comparison circuit and a data input of the first register, which vkod, a second input coupled to the comparison circuit, the input resolution reading the first register is connected to the second input of AND and inverted output five 0 5 0 5 40 5,,, s The third trigger, the direct output of which is connected to the enable inputs of the first and second registers, the installation input of the third trigger is connected to the output of the comparison circuit, the input of the comparison implementation which is connected to the output of the And element, and the reset input of the third trigger , with the reset input of the second trigger and the first input of the OR element, the output of which is connected to the installation input of the first trigger, the second input of the OR element is the device start input, information input A control unit is connected to an output of a block of adders, the first group of inputs of which is connected to a group of outputs of a production / operating costs unit that contains a group of shunt resistors, a matrix of cost setting cells, each of which contains a key, a setpoint generator, a load resistor, and a diode, anode which is the output of the costing cell, and the cathode is connected to the output of the key, the control input of which is the control output of the costing cell, the information input of the key is connected to the output of the movable ontack of the setter and the first output of the load resistor, the second outputs of which are grounded, and the first output of the setter constitutes the master input of the costing unit, the outputs of the costing cells of each matrix column are combined and form the corresponding output of the output group of the production and operating costs unit and connected to the first output of the corresponding the shunt resistor, the second inputs of which are connected to the integrated master inputs of the cost task cells and connected to the common power supply bus of the device The inputs of the cost task cells of each row of the matrix are combined and form the i-th input of the group of inputs of the production and operating costs unit, which is connected to the corresponding output of the control unit and the corresponding i-input of the initial cost unit, consisting of m initial cost task cells, each of which consists of a key and a setpoint, the first output of which is grounded, and the moving contact is connected to the key information input, the output of the initial cost reference key is 91517044.0 the output of the initial cost unit and the corresponding cost image that inputs the highlight It is united with the corresponding input of the initial costs, the second conclusions of the group of adders block, control-sensors of the task cells of the initial halls and the lower inputs of the keys of the task cost cells are connected to the power bus.