SU1365003A1 - Measuring device - Google Patents

Abstract

The invention relates to technical physics, namely to devices for digitally measuring the amplitudes of spectrometric pulses a. composition of precision spectrometric systems. The purpose of the invention is to increase the reliability of measurements by reducing the time of uncontrolled operation of the device. A device containing a voltage converter — current, main and leveling converters code — current, comparator, sequential approximation register, three pulse shapers, two registers, a synchronization unit, a counter, two reference voltage sources, and a subtraction unit — three switches are introduced, a generator pulses, a delay element, two triggers and two elements I. Due to the formation of internal inter-testing effects of various elements of the device, information is generated about the degree of its metrological retention. Sgiach parameters under the influence of external destabilizing factors that allows additional control over device functionality in the intervals between the metrological certification E and reduce uncontrolled during its operation. 3 pe. f § (L with about JV

Description

113650032

The invention relates to a physicist, by its outputs, to a numerical bus physics, namely, devices 28 and another group of inputs to corresponding digital measurements of amplitude outputs of register 16. Control electrometry pulses in precision spectrometric systems, and can be used in systems collection of activation-spectrometric information

Tel nuclear reactors.

The purpose of the invention is to increase the measurement accuracy.

Figure 1 shows the functional diagram of the measuring device in FIG. 2 and 3 are time diagrams illustrating his work.

The measuring device (Fig. 1) contains a comparator 1, a main 2 and a leveling 3 code-current transducer, a voltage-current converter 4, 5-7 switches, re, -distor 8 successive approximations, a synchronization unit 9, drivers 10 - 12 pulses , counter -13 sources 14 and 15 of the voltage reference, registers 16 and 17, delay element 18, pulse generator 19, triggers 20 and 21, And elements 22 and 23 subtraction unit 24, information bus 25, mode and readiness buses 27, numeric bus 28, start bus 29 and common bus 30.

The synchronization unit 9 (FIG. 1) contains a trigger 31 and a pulse generator 32, the output of which is the output of the unit and the control input of which is connected to the forward output of the trigger 31, the synchronization input-C of which 5 is the input of the unit start / setting R input which is the blocking input input and the informational D-input of which is connected to the bus of the logical unit (not indicated).

The output of the converter 4 voltage - current is connected to the outputs of the main 2 and leveling 3 converter code - current and through the comparator 1 to the information input of the register B successive approximations, the installation input of which is connected to the start input of the synchronization unit 9 and to the counting input of the counter 13 connected These outputs to the corresponding information inputs of the screeding converter 3 code - current and register 17, the outputs of which are connected to the first group of inputs of the subtractor 24, are connected

register output 8

The target approximations are connected through the pulse shaper 10 to the synchronization inputs of registers 16 and 17 to the pulse shaper 1 1 input and to the blocking input of the synchronization unit 9, the output of which is connected to the synchronization input of the 8 successive approximation register, the bit outputs of which are connected to the information inputs converter 2 code - current and register 16. The output of the first source 14 of the reference voltage is connected to the reference input of the main converter 2 code - current and to one input of the switch 7 connected another input - to the output of the source 15 of the reference voltage and output - to the reference input of the scaling converter 3 code - current. The delay element 18 is connected by an input to the mode bus 26, to the pulse driver input 12 and to the control inputs of switches 5 and 6 and the output to one inputs of elements 22 and 23, to the set inputs of trigger 20 and 21, and to the control input of pulse generator 19 whose output is connected to one input of switch 6,

connected by another input to the bus 29 start and the output to the start input of the synchronization unit 9. The output of the pulse shaper 12 is connected to the installation input of the counter 13,

connected overflow output to the clock input of the trigger 21, the forward output of which is connected to the clock input of the trigger 20 and to the second input of the And 22 element connected by the output to the setup input of the register 16. The inverted output of the trigger 21 is connected to the second input of the And 23 element connected by the third input to the third input element

Both 22 and to the direct output of the trigger 20 and the output to the setup input of the register 17 and to the control input of the switch 7. The input of the voltage converter 4 is a current connected to

the output of the switch 5, the first and second inputs of which are connected respectively to the information bus and the common bus 30.

The voltages of the sources 14 and 15 of the reference voltage are selected from a ratio of 7 and (1 + D), where D2 is the differential nonlinearity of the transformation of the main converter. 2 code is the current.

In Fig. 2, the following designations are accepted: the signal 33 of the logical O on the mode bus 26, the pulses 34 at the output of the generator 19 pulses, the signal 35 at the direct output of the trigger 21, the signal 36 at the output of the trigger 20, the signal 37 at the output of the And 22, the signal 38 at the output of the element 23, the signal 39 on the start bus 29, the signal 40 at the counting input of the counter 13, the signal 41 at the start input of the synchronization unit 9, the signal 42 at the synchronization input of the register 8 consecutive approximations, the signal 43 at the output of the driver 10, signal 44 at the output of register 16, signal 45 at the output of register 17, si nal 46 to wordline 28, a signal 47 at the output of the pulse shaper 11, a signal 48 at the output of shaper 12, the signal at the output 49 of the counter 13 overflows, the signal 50 at the output 18 of the delay element.

The measuring device operates in two modes - in the conversion mode and in the control mode.

The signal from the information bus 25 through the switch 5 and the converter 4 voltage - the current flows to the input of the comparator 1, where it is algebraically summed with the equalizing current of the equalizing converter 3 code - current and with the opposite current of the main converter 2 code - current. The sign of this sum is determined at each time point by comparator 1 and transmitted to the information input of register 8 of successive approximations. The triggering pulse from the start bus 29 (Fig. 2, POS. 39 through the switch 6 is fed to the setup input of the register 8 of successive approximations, to the counting input of the counter 13, set it in the state X, (Fig. 2, pos. .40 and through the start input of the synchronization unit 9 to the synchronization input of the trigger 31 translate it on the falling edge into a single state (FIG. 2 PO3.41). The signal from the output of the trigger 3 is fed to the input of the gene control 40

To set the device to the conversion mode on the bus 26 of the for-jg rator mode, 32 pulses, the pulses with are extracted by a logical O (Fig. 2, whose stroke (Fig. 2, pos.42) via pos.33) arriving at the inputs control switches 6 and 5 and through the delay element 18 to the input of the control of the pulse generator 19, to the setup inputs of the flip-flops 21 and 20 and to the first inputs of the And 22 and 23 elements. The output of the switch 6 is connected to the start bus 29, the output of the switch 5 is connected to information bus 25, the pulses at the output of the generator 1 9 pulses are absent (figure 2, p C.34), logical 1 is set at the direct output of flip-flop 21 and at the output of flip-flop 20 (FIG. 2, pos.35 and 36, respectively), a logical O is installed at the output of element 22 (Fig. 2, pos.37), arriving at the setup input register 16, and the output element. And, 23 also sets the logical output of the synchronization unit 9 to the synchronization input of the register 8 successive approximations. In this case, the signals from the bit outputs of the register of 8 successive approximations arrive at both the information inputs of the main code converter and the current for performing the analog-to-digital conversion process itself and the information inputs of the register 16. After the conversion process at the control output of the register 8 is completed by

50 consecutive approximations are produced by the signal that triggers the driver 10, the pulse from the output of which (figure 2, pos. 43) arrives at the synchronization input of register 16, registers a certain number Y resulting from analog-digital conversion, (figure 2 , pos.44 n the input of the synchronization register 17, registering the incoming on its informative O (figure 2, pos.38), arriving at the installation input of the register 17 and the input of the switch control

five

ten

15

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7, as a result of which its code closes with the first input and the reference voltage from the output of source 14 of the reference voltage goes both to the input of the main converter 2 code - current and to the input of equalizing converter 3 code - current.

The signal from the information bus 25 through the switch 5 and the voltage converter 4 - the current is fed to the input of comparator 1, where it is algebraically summed with the equalizing current of the equalizing converter 3, the code is the current and the current opposite to the current of the main converter 2 is the current. The sign of this sum is determined at each time point by comparator 1 and is transmitted to the information input of register 8 of successive approximations. The triggering pulse from the start bus 29 (FIG. 2, pos. 39) through the switch 6 is fed to the installation input of the register 8 successive approximations, to the counting input of the counter 13, set it to some state X, (FIG. 2, pos. 40 ) and through the start input of the synchronization unit 9 to the synchronization input of the trigger 31, it is transferred along the trailing edge into a single state (Fig. 2, PO3.41). The signal from the trigger output 31 is fed to the input of the gene control20

25

thirty

-jg rator 32 pulses, the pulses from the output of which (figure 2, pos.42) through

rator of 32 pulses, the pulses from the output of which (FIG. 2, pos. 42) through

the output of the synchronization unit 9 is fed to the synchronization input of the register 8 successive approximations. In this case, signals from the bit outputs of the register 8 of successive approximations are received both at the information inputs of the main code converter - the current for carrying out the analog-digital conversion process itself and at the information inputs of the register 16. After the conversion process at the control output of the register 8 successive approximations is completed a signal is generated that triggers the driver 10, the pulse from the output of which (FIG. 2, pos. 43) is fed to the synchronization input of the register 16, registering the received in p result of analog-to-digital conversion Nektorov number Y, (2, poz.44 to the clock input of register 17, registers incoming on its infort

operating inputs number X (FIG. 2, pos. 45), 11 pulses to the input of the driver, as well as to the lock input of the synchronization unit 9 and further to the installation input of the trigger 31, transferring the latter to the zero state (FIG. 2, pos. 41 ) and blocking the oscillation of the pulses by the generator 32 (figure 2, pos.42). The information from the outputs of registers 16 and 17 goes to the corresponding groups of inputs of subtraction unit 24, the outputs of which form the code of the number Z, Y, - X arriving at the number bus 28 (FIG. 2, pos. 46). A pulse front pulse pulse generator 10 (FIG. 2, pos. 43) starts the pulse former 11, the pulse from the output of which (FIG. 2, pos. 46) goes to the ready 27 bus, signaling the readiness of the code on the numeric bus 28 This signal is transmitted to an external device.

For an operational check of the operability of the measuring device blocks on the mode bus 26, a logical I (FIG. 2, pos. 33) is supplied to the control inputs of the switches 6 and 5, to the input of the delay element 18 and to the input of the driver 12 pulses. At the same time, the output of the switch 16 is connected to the output of the pulse generator 19, the output of the switch 5 is connected to the common bus 30, and the output of the driver 12 is a pulse (figure 2, pos.48), which arrives at the installation input of the counter 13 and sets its in the zero state (FIG. 2, pos. 40) i. At the moment of resetting the counter 13, a voltage drop (FIG. 2, pos. 49) may be generated at its overflow output, arriving at the clock T-input of the trigger 21, however since the installation S-input of this trigger at this moment in time causes logical O sticking out of the output of the delay element 18 (Fig. 2, pos. 50), the state of the flip-flop 21 remains unchanged (Fig. 2, pos. 35. After the corresponding time has elapsed, logical 1 appears at the output of the delay element 18 (Fig. 2 , pos.50), arriving at the installation S-input of the trigger 21, at the installation S-input of the trigger 20, at the control input of the generator 19 pulses, at the inputs of the elements And 22 and 23, set1365003

0

five

the output element 22 and the logical 1 (Fig. 2, pos. 37), which is fed to the setup input of the register 16 and fixes on its outputs a code of the number O (Fig. 2, pos. 44). The pulse from the output of the generator 19 pulses (figure 2, pos.34) through the switch 6 is fed to the counting input of the counter 13, set the code number 01 (figure 2, pos.40), as well as to the start input of the synchronization unit 9, initiating the conversion process. After the conversion is completed, a pulse appears at the output of the pulse driver 10 (Fig. 2, pos. 43), arriving at the synchronization input of the register 17 and fixing the code of the number 01 in it (Fig. 2, pos. 45).

The state of register 17 is fed to one group of inputs of subtracting unit 24. Afterwards, the code of the number 00 arrives at the other group of inputs of the subtraction unit 24;

5 outputs, a code of the number -1 (Fig. 2, pos. 45) is received, arriving at the numeric bit 28. By a pulse from the output of the pulse former 11 (Fig. 2, pos. 47), the status of the numerical bus 28 is detected by an external device. As the pulses from the generator output 19 pulses continue, the counter 13 is successively set to the state 02, 03, ..., p-1 (Fig. 2, pos. 40), the numbers 02, 03, are also recorded in the register 17. ., p-1 (Fig. 2, pos. 45), state 16 is stored in register 16 (Fig. 2, pos. 45), and from the numeric bus 28 to the external device the codes of numbers - 2, -3, ..., 1-n (Fig. 2, pos. 46), the presence of which for an external device confirms the correct functioning.

5, a counter 13, a register 17, and a subtractor 24 (FIG. 2, control 1).

The next pulse from the output of the pulse generator 19 (Fig. 2, pos. 34) sets the counter 13 to the zero state (Fig. 2, Pos. 40). At the same time, the output of the overflow of the counter 13 forms a voltage drop (Fig. 2, pos. 49), which enters the clock T-input of the flip-flop 21 and sets at its direct output the logical O (Fig. 2, pos. 35), the closing element And 22 (figure 2, pos.37), and on the inverse output - logical 1, rykryvayuschy element And 23

0

five

0

0

five

(figure 2, pos.38). Logical 1 from the output of the AND 23 element is fed to the setup input of the register 17 and sets at its outputs a code number 00 (Fig. 2, pos. 45), assigned to one group of inputs of the subtraction unit 24. In addition, the signal d of the output element And 23 is fed to the control input of the switch 7, while the output from the source 15 of the reference voltage through the switch 7 is fed to the input of the reference voltage of the equalizing converter 3 code - current, increasing its conversion factor in ( 1 + D,) times. However, since the code outputs of code 13 (figure 2, pos. 45) arrive at the output outputs of scribing converter 3 code — the current in this case, the output value of the latter is set to zero leveling current. From the common bus 30 through the switch 5 to the input of the converter 4 is the voltage — the current is supplied to the zero voltage level, therefore the zero current is supplied from the output of the latter.

After the analog-digital conversion process initiated by the pulse from the output of the pulse generator 19 is completed (Fig. 2, pos. 34), the code of number 00 (Fig. 2, pos. 44) arrives at the corresponding input group of the subtractor 24; the outputs of which the same code enters the numerical bus 28 (FIG. 2, pos. 46) and is signaled by the readiness bus 27 (FIG. 2, pos. 47) by an external device. The second pulse from the output of the pulse generator 19 sets the counter 13 to the state 01, and after completion of the analog-digital conversion from the word line 28 to the external device goes to; a certain number Z lying in the vicinity of the number (1 + Dj). After the third pulse arrives from the output of the pulse generator 19, the code of the number ZK lying in the vicinity of the number 2 (), etc., is formed in the same way after the arrival of the nth pulse from the output of the pulse generator 19, in the counter 13 a code of the number (n-1) is formed (FIG. 2, pos. 40), and on the number bus 28 - the code of the number Z,

five

0

five

Q

0

with

five

0

five

0

the number lying in the neighborhoods (n-1) (1 + D.,) (Fig. 2, pos. 46).

Thus, despite the substantial non-linearity of the conversion of the main code-to-current converter 2, from the numerical bus 28 to the external device, a sequence of increasing numbers Z appears, the presence of which for the external device confirms the correct operation of the equalizing converter 3 code-current (Fig. 2, control 2).

The next pulse from the output of the pulse generator 19 (Fig. 2, pos. 34) again sets the counter 13 to the state 00 (Fig. 2, pos. 40). At the same time, at its overflow output, a voltage drop is formed (Fig. 2, pos. 49), which enters the clock T-input of the flip-flop 21 and establishes logical I at its direct output (Fig. 2, pos. 35). The signal from the output of the trigger 21 is fed to the clock T-input of the trigger 20 and sets at its output a logical O (FIG. 2, pos. 36), which enters the inputs of the elements And 22 and 23 and closes them (FIG. 2, pos. 37 and 38, respectively), removing the setup signal from register input 1 7 and connecting the output of switch 7 to the output of reference voltage source I4. Upon completion of the analog-to-digital conversion process, a code for the number Z 00 (Fig. 2, pos. 46) is generated on the word line 28, which is recorded by an external device by a signal from the readiness bus 27 (Fig. 2). The next pulse from the pulse generator 19 code sets the counter 13 to the state 01, after the conversion is completed, the code 17 is recorded in register 17, and in register 16 the conversion result code Y, whose value lies within 1 t J, where L is the total error (in quanta) of the main 2 and leveling 3 converters the code is current. At the same time, the result of measuring Z as a number Z 0 t is formed on the number bus 28.

Upon further receipt of the pulses from the output of the pulse generator 19 (FIG. 2, pos. 34), the device operates in a similar way, forming the family of numbers Z

the limits of Q and, the presence of which for an external device confirms the presence of a leveling converter on the reference input; the 3 code is the voltage from the output of the source 14 of the reference voltage (Fig. 2, control 3).

Thus, if after performing all three control operations in the external device, the expected results are obtained, we can assume that the blocks of the measuring device function properly, and the information obtained earlier does not contain a false component. In this case, a logical 1 (Fig. 2, pos. 33) can be set again on the mode bus 26, which returns the device to the measurement mode.

The use of the invention makes it possible, by using a new operation to check the operability of the units of the measuring device, to significantly reduce the time of its uncontrolled operation and, consequently, reduce the likelihood of obtaining false information.

Claims (1)

 Invention Formula Measuring device containing the main and scaling converters code - current, comparator, serial approximation register, counter, subtractor, three pulse drivers, two registers, synchronization unit, two reference voltage sources, numeric bus, readiness bus, data bus, mode bus , start bus, common bus and voltage converter - current, the output of which is connected to the outputs of the main and leveling converters code - current and through a comparator - to the information input of the register approximate input, the setup input of which is connected to the trigger input of the synchronization unit, and the counter input connected to the corresponding information inputs of the scaling converter code-current and the first register, whose inputs are connected to the first group of inputs of the subtractor connected by its own outputs to numeric bus and another group of inputs to the corresponding outputs of the second register, the control output of the register of successive approximations is connected via the first pulse shaper to the synchronization inputs of the first and second registers, to the input of the second pulse shaper and to the input 0 of the lock of the synchronization block, the output of which connected to the synchronization input of the register of successive approximations, the bit outputs of which are connected to the information 5 inputs of the main converter code - current and the second register, the output of the first Source of the reference voltage connected to the reference input of the main converter code - current, 0 characterized in that, in order povsh1eni - measurement reliability, commutation three introduced therein -. torus, two triggers, two elements AND, a pulse generator and a delay element, connected to the mode bus, to the input of the third pulse generator, and to the control inputs of the first and second terminal, and the output to the same inputs of both elements AND, 0 to the installation inputs of both triggers and to the control input of the pulse generator, the output of which is connected to one input of the first switch connected to the start bus by another input and to the start input of the synchronization unit, the output of the third pulse generator is connected to the counter installation input, li ne overflow outlet to 0 clock input of the first flip-flop, the direct output of which is connected to the clock input of the second trigger and to the second input of the first element I connected to the installation input of the second register; the inverse output of the first trigger connected to the second input of the second element I connected by the third input to the third input of the first element I and 0 to the direct output of the second trigger and the output to the setup input of the first register and to the control input of the third switch connected to the first and second inputs, respectively, 5 to the outputs of the first and second source the reference voltage and the output to the reference input of the scaling converter code is the current, the input of the voltage converter is the current of connection5 1365003 2 it with the output of the second switch, ration and common buses, and the output of the first and second inputs of which are connected to the second pulse driver are respectively connected with the information keys to the ready nut. IS