SU1257698A1 - Vector generator - Google Patents

Abstract

The invention relates to computing and automation, in particular to devices displaying graphical information on a CRT. The aim of the invention is to increase the reliability and simplification of the vector generator. The generator contains a block of normalization of codes of increments of coordinates, two adders, two converters of codes of increments of coordinates, a converter of reference codes, a summing amplifier, a converter of a compensating code, a reversible counter, two AND elements, a trigger, two converters of coordinate codes, two integrators and a comparator. In the vector generator, the difference in the integration time constant in the X and Y channels is determined with the help of an integrator and a trigger, and eliminated with the help of two AND elements, a reversible counter, a compensating code converter, and a summing amplifier. 3 il. I (Lyu SP Od So CX)

Description

one

The invention relates to computing and automation, in particular, to devices displaying graphical information on a CRT.

The purpose of the invention is to increase the reliability and simplify the vector generator.

On fng. 1 shows a schematic diagram of a vector generator; Fig.2 is a block diagram of a comparator; in fig. 3 - block diagram of the block nomination increments.

The generator contains block 1 of normalization codes of coordinate increments, the first 2 and second 3 adders, the first 4 and second 5 converters of coordinate increment codes, the converter 6 reference codes, the summing amplifier 7, the converter 8 of the compensating code, the reversible counter 9, the first 10 and the second 11 I elements, trigger 12, first 13 and second 14 converters of co-code codes, first 15 and second 16 integrators, comparator 17, bus 18 for the integration start commands, comparators 19 and 20 of the X and Y channels, logic block 21, control driver 22 present signal, the first 23 and second 24 elements AND, an OR gate 25, NOT element 26, AND gate 27, resistor 28, capacitor 29 ..

Block 1 normalization consists of two elements EXCLUSIVE OR 30 and 31, signal generator 32, element And 33, counter 34, two :. reversible registers 35 and 36, memory block 37, made in the form of ROM.

The outputs of the digital storage device (not shown) are connected to the inputs of block 1 normalization of codes of increments of coordinates and adders 2 and 3, the outputs of which through the corresponding converters 13 and 14 codes of the coordinates of the end point of the vector are connected to the inputs of the initial installation of integrators 15 and 16, as well as the third and the fourth inputs of the comparator 17, the other inputs of which are connected to the outputs of the integrators 15 and 16, the control inputs of which are connected to the outputs of the converters 4 and 5 of the coordinate increment codes, the digital inputs of which dineny from the first output unit normalization 1, the control output is connected to the input of the converter 6, the reference codes, the output cos

dinen with the reference input of the converter 5 codes increments of coordinates and through the second input of summing amplifier 7 with the input of converter 4 codes of increments of coordinates, the first input of summing amplifier 7 is connected to the output of converter 8 of the compensating code, the input of which is connected to the output of the reverse counter 9, the inputs of which are connected to the outputs of the first 10 and second 11 elements And, the second inputs of which are connected to the control output of the comparator 17, which is also connected to the digital inputs of the integrators 15 and 16 and to the counting input m trigger 12, the third inputs connected to the outputs of channels X, Y the comparator 17 and the first inputs connected respectively to the direct and inverse outputs of the flip-flop 12.

The generator works as follows.

From a digital storage device (not shown), codes of maximum increments iX and and Y are received simultaneously at block 1 of the normalization of codes of coordinate increments and adders 2 and 3 of accumulating type.

After testing the codes in block 1 and converting them into converters 4.5 and 6, codes are entered from adders 2 and 3 to converters 13 and 14. At the same time, a start pulse enters the start command bus 18, which results in the comparator 17 converting integrators 15 and 16 into integration mode. In this mode, sawtooth voltages are formed at the outputs of the integrators 15 and 16, the direction and speed of which is determined by the magnitude and sign of the voltages coming from the outputs of the converters 4 and 5.

After the voltage at the output of the integrators 15 and 16 is compared with the voltage of the corresponding converter 13 and 14, the comparator 17 generates a signal that leads the integrators 15 and 16 to the initial conditions mode. At the same time, the comparator 17 generates signals for the elements of And 10 and 11 and the trigger 12. With different constant integration in the X and Y channels, the operation of the Comparators 19 and 20 of these channels occurs at different points in time, and the difference is greater when the speeds differ integrated.

This causes an error at the junction of vectors.

At the beginning of the integration rate correction process, the integrators 15 and 16 are switched to the initial conditions mode by the signal of the comparator 19 of the channel X. This analyzes the state of the comparator 20 of the channel U at its output U. Then vice versa

The installation of the integration mode and transfer of the integrators 15 and 16 to the initial conditions setting mode is performed according to the signal of the comparator 20 of the channel U. This analyzes the state of the comparator 19 of the X channel at its output X Trigger 12 operates in the counting mode by switching the AND 10 and 11 elements. As the counting pulses, signals coming from the output of the comparator 17 are used. In the first step of the correction step, the element 11 is opened and the element 10 is closed, and in the second cycle the element 10 is opened and the element 11 is closed.

If the integration speed in channel X is higher than in channel Y, then by the time the comparator 19 of channel X is triggered and produces a zero logic signal, a high level at the output of comparator channel 20 will show a discrepancy or error.

At the same time, the signal of comparator 17 passes through the open element I 11 and causes a corresponding change in the code at the output of the reversible counter 9. The changed code state at the output of the reversible counter 9 causes a change in voltage at the output of converter 8 and, accordingly, at the output of summing amplifier 7 connected to the reference input converter 4 codes increments ko-. the ordinates of channel X, which leads to a decrease in the voltage level at the input of the integrator 15 and to a decrease in the integration rate of channel X. If the integration speed in channel Y is higher than in channel X, the signal of comparator 17 will pass through the open element And 10, causing a code change at the output of the reversible counter 9, leading to an increase in the voltage level at the input of the integrator 15 and to an increase in the integration speed of the channel X.

Described push-pull mode of operation of the node speed correction integra

five

20

0

5 0 5

0

five

This is possible due to the slow variation of this velocity under the influence of external climatic factors.

The accuracy of the correction assembly is determined only by the sensitivity of the comparator 17 and is independent of other circuit elements. In the generator, automatic correction of the channel integration rate can be performed periodically at the beginning of the regeneration frame.

If the integration speeds in channels X and Y are increased, then the correction circuit is turned on. I,

The transition to the push-pull correction mode allows you to reject a number of elements of the prototype, which simplifies the scheme and increases reliability.

Claims (1)

Invention Formula The vector generator containing the block of normalization of codes of increments of coordinates, the first and second inputs of ko-. Secondly, the first and second inputs of the device, respectively, which are connected respectively to the inputs of the first and second adders, the first and second outputs of the block of normalization codes of increments of coordinates are connected to the first inputs of the first and second converters of codes of increments of coordinates, the third output of the block of codes of increments of coordinate increments is connected to the input of the converter of reference codes, the outlet of which is connected to the second input of the second converter of the codes of increments of coordinates and to the first one ode summing amplifier whose output is connected to the second input of the first transducer increments codes coordinates .vtoroy input of the summing amplifier is connected to  the output of the converter of the compensating code, the input of which is connected to the output of the reversible counter, the first and second inputs of which are connected to the outputs of the first and second And elements respectively, the first input of the first And element is connected to the first output of the trigger, the outputs of the first and second adders are connected respectively through the first and second  Coordinate codes to the first inputs of the first and second integrators, respectively, the second the inputs of which are connected to the outputs of the first and second converters of the coordinate increment codes, the third inputs of the first and second integrators are connected to the first output of the comparator, the output of the first integrator is the first generator output connected to the first input of the comparator, the second input of which is connected to the output of the second integrator, which is the second output of the generator, the third and fourth inputs of the comparator are connected to the outputs respectively sh lu the first and second coordinate code converters, the fifth input of the comparator is the third generator input, characterized in that that, in order to increase reliability and simplify the generator, the first output of the comparator is connected to the trigger input and to the second inputs of the first and second elements And, the second output of the trigger is connected to the first input of the second element And, the second and third outputs of the comparator are connected to the third inputs of the first and second element I. omtS oarfS Compiled by L.Abrosimov Editor E.Kopcha Tehred P.Oleinik Proofreader V.Sinitsa Order 4963/50 Circulation 455 Subscription VNISh State Committee of the USSR for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production printing company, Uzhgorod, Projecto st., 4 .З