SU981981A1 - Device for input pickup data - Google Patents

Description

register, the third input of which is connected to the first output of the second memory block, the third input of which is connected to the first output of the first register, the fourth input of which is connected to the output of the second register, which is connected to the output of the adder, the first input of which is connected to the second output of the first register and the input of the third register, the output of which is connected to the second input of the adder, the output of the second decoder is connected to the second input of the encoder, the output of the switch is connected to the fifth input of the first register, the fourth input of the second unit the memory device is input and the second output of the second block pgil ti is the output device. Introducing the specified blocks and new connections allows, upon request from the digital computer, to instantly output information on all simultaneously or a segment of the requested channels, each of which is formed by a sensor, an analog-to-pulse conversion unit, and a counter. In the device, the time required for entering information is determined only by the information processing time in the digital computer and the time of one analog value conversion to code. At the same time, the asynchrony of the exchange between the digital computer and the production circuits does not affect the speed of the device, there is no waiting time, and the information in the digital computer is received by arrays, which reduces the number of digital computer calls to one. An additional positive effect of the device is an increase in the accuracy of solving the problem by reducing the dynamic error, since reducing the time to solve the problem increases the frequency of quan. tovany in time. - In FIG. 1 shows a block diagram of the device; in fig. 2 - control unit. The device contains a control unit 1, the odds (converter 2 sinusoidal voltage, the first counter (channels) 3 and the second counter (operations) 4, analog-to-digital converter 5 and the first register (reception) b, sensors 7, the first decoder 8, second memory block 10, switch 5 9 and first memory block 11, group of counters 12, encoder 13, second decoder 14, adder 15, third register (storage) 16, second register (result) 17, pulse generator 18, trigger start conversion 19, frequency divider 20, third decoder 21, and a set of triggers 22 and 23, trigger conditions of the transitions 24 and the small cycle trigger 25. The device works as follows: The analog information of each sensor 7 is converted into a code in parallel across all channels. When turning on the power, as in the case of failure, the work starts on a small cycle (the Tg 25 works in control 1), i.e., only information is written off from the coarse counting counters for two-digit values and from single-value counters via the reception register b to the second memory block 10. Channels are sampled by channel counter 3, ne The first decoder 8 and the commutator 9. Operation counter 4 together with the second decoder 14 form the command Removing information from the converters to the receive register b and overwriting the receive register b into the second Psm unit 10. Thus, in the cells of the block, channels: a slowly varying piece of information (coarse reading) for two-count values and single-count information. The address code for the second memory block 10 forms the same counter of channels 3 and the first decoder 8. After the passage of the program of the small cycle, work begins on a large or full cycle. Here the trigger of 24 conditional transitions comes into operation. By the single-counting condition, which forms the first block of 11th unit, the control unit starts a trigger of 24 conditional transitions, which generates a control signal and sets the counter 4 forcedly forced into a state that determines the number of commands needed to process information . By the condition of two-counting, formed by the same first II block, the control block 1 together with the operation counter 4, the second decoder 14, the diffuser 13 forms the complete algorithm for the operation of the double-digit variable. Depending on the features generated by the first memory block 11, the control unit 1 (the trigger of conditional transitions) creates different combinations of forced writing to the counter 4 operations, as a result of which the number of instructions in the algorithm changes. Simultaneously with this, during the execution of the program, a 3-channel counter is corrected to read information into the receive register 6 on a coarse count from the second memory block 10. The third register (information storage) 16, the adder 15 and the second register (result) 17

serve for the addition of r necessary for stitching codes of coarse and precise counting; - D result of the commands in the second memory block .10 writes the code of the two-counting code with its address, formed by the channel counter 3. The value of the code information corresponds to the actual position of the sensors 7

In this device, the time taken to perform an analog-to-digital conversion (which in the prototype is measured in milliseconds) is not included while waiting for information after the DVR request. The device displays an instant readiness for exchange. Digital computer with any information set. Thanks to that. increased dysfunction and improved dynastic characteristics of analog-to-digital mating.

.Foomula invention

A device for inputting information from sensors containing, analog-to-digital converters, a switch, a first register, an ypee unit and a sinusoidal voltage driver, characterized in that, in order to increase the speed of the device, sequentially connected first decoder and the first counter are entered into it whose input is connected to the first output of the control unit, serially connected to the decoder and the second counter, the input of which is connected to the output of the control unit, the third output of which is connected to the first input m first register, a group of counters whose inputs are connected to outputs of analog-to-digital converters, and the outputs are connected

the switch inputs, the adder, the second and third registers, the first and second memory blocks; the fourth output of the control unit is connected to the input of a sinusoidal voltage generator, the output of which is connected to the sensor inputs, the outputs of the horns are connected to the first inputs of analog-to-digital converters, the second inputs of which are connected to the fifth output of the control unit, the input of which is connected to the first input of the encoder and the output of the first memory block, the input of which is connected to the output of the first decoder, the input of the switch and the first input of the second memory block, the second input of which is connected to the outcome of the encoder and the second input of the first register, the third input of which is connected to the first output of the second memory block,

0 the third input of which is connected to the right output of the first register, the fourth input of which is connected to the output of the second register, whose input is connected to the output of the adder, the first input of which is connected to the second output of the first register and the input of the third register, whose output is connected to the second input of the adder , the output of the second decoder is connected to the second input of the encoder, the output of the commutator is connected to the fifth input of the first register, the fourth input of the second memory block is the device input, and the second output of the second

5 of the memory block is the output of the device ..

Sources of information taken into account in the examination

40

1. Author's certificate of the USSR 802955, cl. G About F 3/00, 197.9.

2. USSR author's certificate

1 824180, class G 06 F 3/00, 1978 (prototype).

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Claims (1)

Foomula inventions A device for inputting information from sensors, containing analog-to-digital converters, a switch, a first register, a control unit and a sinusoidal voltage generator, characterized in that, in order to increase the speed of the device, the first decoder and the first counter are connected in series which is connected to the first output of the control unit, sequentially connected to a decryptor and a second counter, the input of which is connected to the second output of the control unit, the third output of which is connected to the first input of the first register, a group of counters, the inputs of which are connected to the outputs of analog-to-digital converters, and the outputs are connected to the inputs of the switch, the adder, the second and third registers, the encoder, the first and second memory blocks, and the fourth output of the control unit is connected to the input of the sinusoidal shaper voltage, the output of which is coupled to inputs _f sensors whose outputs are connected to first inputs of analog-to-digital converters, the second inputs of which are connected to the fifth output of the control unit, the input of which connected to the first input of the encoder and the output of the first memory block, the input of which is connected to the output of the first decoder, the input of the switch and the first input of the second memory block, the second input of which is connected to the output of the encoder and the second input of the first register, the third input of which is connected to the first output of the second block memory, the third input of which is connected to the first output of the first register, the fourth input of which is connected to the output of the second register, the input of which is connected to the output of the adder, the first input of which is connected to the second the first register and the input of the third register, the output of which is connected to the second input of the adder, the output of the second decoder is connected to the second input of the encoder, the output of the · mutator is connected to the fifth input of the first register, the fourth input of the second memory block is the input of the device, and the second output of the second the memory block is the output of the device.